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hcs08 microcontrollers freescale.com mc9s08gb60a mc9s08gb32a mc9s08gt60a mc9s08gt32a data sheet mc9s08gb60a rev. 2 07/2008

mc9s08gb60a data sheet covers: mc9s08gb60a mc9s08gb32a mc9s08gt60a mc9s08gt32a mc9s08gb60a rev. 2 07/2008
mc9s08gb60a data sheet, rev. 2 6 freescale semiconductor revision history to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earl ier revision. to verify you ha ve the latest information available, refer to: http://freescale.com the following revision history table summar izes changes contained in this document. revision number revision date description of changes 1.00 07/14/2005 initial public release. 1.01 09/04/2007 added a footnote to rti of table 3.2; added rti description to section 3.5.6; added a sentence "if active bdm mode is enabled in stop3, the internal rti clock is not available." to the section 5.7 real time interrupt. 1.02 02/25/2008 changed the maximun low power of fbe and fee in ta b l e a - 9 to 10 mhz. changed the title of ta b l e 1 3 - 2 from ?iic1a register field descriptions? to ?iic1f register field descriptions? 2 7/30/2008 added 42-pin sdip information. changed ?however, when hgo=0, the maximum frequency is 8 mhz in fee and fbe modes.? to ?however, when hgo=0, the maximum frequency is 10 mhz in fee and fbe mo des.? in appendix b5. updated the ?how to reach us? at backpage. this product incorporates superflash ? technology licensed from sst. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. ? freescale semiconductor, inc. , 2005-2008. all rights reserved.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 3 list of chapters chapter number title page chapter 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 pins and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 chapter 4 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 5 resets, interrupts, and system co nfiguration . . . . . . . . . . . . . . . 65 chapter 6 parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 7 internal clock generator (s08icgv2) . . . . . . . . . . . . . . . . . . . . . 103 chapter 8 central processor un it (s08cpuv2) . . . . . . . . . . . . . . . . . . . . . . 129 chapter 9 keyboard interrupt (s 08kbiv1) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 chapter 10 timer/pwm (s08tpmv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 chapter 11 serial communications interfa ce (s08sciv1) . . . . . . . . . . . . . . 171 chapter 12 serial peripheral in terface (s08spiv3). . . . . . . . . . . . . . . . . . . . 189 chapter 13 inter-integrated circuit (s08iicv1) . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 14 analog-to-digital converter (s08at dv3) . . . . . . . . . . . . . . . . . 223 chapter 15 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 appendix a electrical characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 appendix b eb652: migrating from the gb60 series to the gb60a series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 appendix c ordering information and mech anical drawings . . . . . . . . . . 287

mc9s08gb60a data sheet, rev. 2 freescale semiconductor 7 chapter 1 device overview 1.1 overview ................................................................................................................... ......................17 1.2 features ................................................................................................................... ........................17 1.2.1 standard features of the hcs08 fami ly .........................................................................17 1.2.2 features of mc9s08gbxxa/gtxxa series of mcus ....................................................18 1.2.3 devices in the mc9s08gb xxa/gtxxa series ...............................................................19 1.3 mcu block diagrams ......................................................................................................... ............19 1.4 system clock di stribution .................................................................................................. ............21 chapter 2 pins and connections 2.1 introducti on ............................................................................................................... ......................23 2.2 device pin assi gnment ...................................................................................................... .............24 2.3 recommended system connections ............................................................................................. ..27 2.3.1 power .................................................................................................................... ...........29 2.3.2 oscillator ............................................................................................................... ...........29 2.3.3 reset .................................................................................................................... ............29 2.3.4 background / mode select (ptg0/bkgd/ms) ..............................................................30 2.3.5 general-purpose i/o and peripheral ports .......................................................................30 2.3.6 signal propertie s summary .............................................................................................32 chapter 3 modes of operation 3.1 introducti on ............................................................................................................... ......................35 3.2 features ................................................................................................................... ........................35 3.3 run mode ................................................................................................................... .....................35 3.4 active backgr ound mode ..................................................................................................... ..........35 3.5 wait mode .................................................................................................................. .....................36 3.6 stop modes ................................................................................................................. .....................36 3.6.1 stop1 mode ............................................................................................................... .......37 3.6.2 stop2 mode ............................................................................................................... .......37 3.6.3 stop3 mode ............................................................................................................... .......38 3.6.4 active bdm enabled in stop mode ................................................................................38 3.6.5 lvd enabled in stop mode .............................................................................................39 3.6.6 on-chip peripheral modules in stop modes ...................................................................39 contents section number title page
mc9s08gb60a data sheet, rev. 2 8 freescale semiconductor section number title page chapter 4 memory 4.1 mc9s08gbxxa/gtxxa memory map ..........................................................................................43 4.1.1 reset and interrupt vect or assignments ..........................................................................43 4.2 register addresses a nd bit assignments ..................................................................................... ...45 4.3 ram ........................................................................................................................ ........................50 4.4 flash ...................................................................................................................... ..........................50 4.4.1 features ................................................................................................................. ...........51 4.4.2 program and erase times ................................................................................................51 4.4.3 program and erase command execution ........................................................................52 4.4.4 burst program ex ecution .................................................................................................5 3 4.4.5 access erro rs ............................................................................................................ .......55 4.4.6 flash block pr otection ................................................................................................... ..55 4.4.7 vector redire ction ....................................................................................................... ....56 4.5 security ................................................................................................................... .........................56 4.6 flash registers and control bits ........................................................................................... ..........57 4.6.1 flash clock divider re gister (fcdiv) ...........................................................................57 4.6.2 flash options register (fopt and nvopt) ...................................................................59 4.6.3 flash configuration register (fcnfg) ..........................................................................60 4.6.4 flash protection register (fprot and nvprot) .........................................................60 4.6.5 flash status register (fstat) ........................................................................................62 4.6.6 flash command register (fcmd) ..................................................................................63 chapter 5 resets, interrupts, and system configuration 5.1 introducti on ............................................................................................................... ......................65 5.2 features ................................................................................................................... ........................65 5.3 mcu reset .................................................................................................................. ....................65 5.4 computer operating prope rly (cop) watchdog .............................................................................66 5.5 interrupts ................................................................................................................. ........................66 5.5.1 interrupt stack frame .................................................................................................... ..67 5.5.2 external interrupt re quest (irq) pin ..............................................................................68 5.5.2.1 pin configurati on options ..............................................................................68 5.5.2.2 edge and level se nsitivity .............................................................................69 5.5.3 interrupt vectors, sources , and local ma sks ..................................................................69 5.6 low-voltage detect (lvd) system ............................................................................................ ....71 5.6.1 power-on reset op eration ..............................................................................................71 5.6.2 lvd reset oper ation ...................................................................................................... .71 5.6.3 lvd interrupt op eration .................................................................................................7 1 5.6.4 low-voltage warning (lvw) .........................................................................................71 5.7 real-time interr upt (rti) .................................................................................................. .............71 5.8 reset, interrupt, and system contro l registers and control bits ...................................................72 5.8.1 interrupt pin request status and control register (irqsc) ...........................................73
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 9 section number title page 5.8.2 system reset status register (srs) ................................................................................74 5.8.3 system background debug force re set register (sbdfr) ...........................................75 5.8.4 system options register (sopt) ....................................................................................76 5.8.5 system device identification register (sdidh, sdidl) ...............................................77 5.8.6 system real-time interrupt status and control register (srtisc) ...............................78 5.8.7 system power management status a nd control 1 register (spmsc1) ..........................79 5.8.8 system power management status a nd control 2 register (spmsc2) ..........................80 chapter 6 parallel input/output 6.1 introducti on ............................................................................................................... ......................81 6.2 features ................................................................................................................... ........................83 6.3 pin descriptions ........................................................................................................... ...................83 6.3.1 port a and keyboard interrupts .......................................................................................83 6.3.2 port b and analog to digital converter inputs ...............................................................84 6.3.3 port c and sci2, iic, and high-current drivers ............................................................84 6.3.4 port d, tpm1 and tpm2 ................................................................................................85 6.3.5 port e, sci1, and spi .................................................................................................... ..85 6.3.6 port f and high-current drivers .....................................................................................86 6.3.7 port g, bkgd/ms, and oscillator ..................................................................................86 6.4 parallel i/o controls ...................................................................................................... ..................87 6.4.1 data direction control ................................................................................................... .87 6.4.2 internal pullup control .................................................................................................. ..87 6.4.3 slew rate control ........................................................................................................ ....87 6.5 stop modes ................................................................................................................. .....................88 6.6 parallel i/o registers and control bits .................................................................................... .......88 6.6.1 port a registers (ptad, ptape, ptase, and ptadd) ................................................88 6.6.2 port b registers (ptbd, ptbpe, ptbse, and ptbdd) ................................................91 6.6.3 port c registers (ptcd, ptcpe, ptcse, and ptcdd) ................................................93 6.6.4 port d registers (ptdd, ptdp e, ptdse, and ptddd) ...............................................95 6.6.5 port e registers (pted, ptepe, ptese, and ptedd) .................................................97 6.6.6 port f registers (ptfd, ptfpe, ptfse, and ptfdd) ..................................................99 6.6.7 port g registers (ptgd, ptgp e, ptgse, and ptgdd) .............................................100 chapter 7 internal clock generator (s08icgv2) 7.1 introducti on ............................................................................................................... ....................105 7.1.1 features ................................................................................................................. .........106 7.1.2 modes of oper ation ....................................................................................................... 107 7.2 oscillator pins ............................................................................................................ ...................107 7.2.1 extal? external reference cl ock / oscillator input ................................................107 7.2.2 xtal? oscillator output ............................................................................................107
mc9s08gb60a data sheet, rev. 2 10 freescale semiconductor section number title page 7.2.3 external clock connections ..........................................................................................108 7.2.4 external crystal/resona tor connectio ns .......................................................................108 7.3 functional description ..................................................................................................... .............109 7.3.1 off mode (o ff) ........................................................................................................... ...109 7.3.1.1 bdm active .................................................................................................109 7.3.1.2 oscsten bit set .........................................................................................109 7.3.1.3 stop/off mode recovery ..............................................................................109 7.3.2 self-clocked mode (scm) ............................................................................................109 7.3.3 fll engaged, internal cl ock (fei) mode .................................................................... 111 7.3.3.1 fll engaged internal unlocked .................................................................. 111 7.3.3.2 fll engaged internal locked ...................................................................... 111 7.3.4 fll bypassed, external cl ock (fbe) mode ................................................................ 111 7.3.5 fll engaged, external clock (fee) mode .................................................................. 111 7.3.5.1 fll engaged external unlocked .................................................................112 7.3.5.2 fll engaged external locked .....................................................................112 7.3.6 fll lock and loss-of-lock detection .........................................................................112 7.3.7 fll loss-of-clock detection ........................................................................................113 7.3.8 clock mode require ments ............................................................................................114 7.3.9 fixed frequency clock ..................................................................................................11 5 7.3.10 high gain oscillator .................................................................................................... ..115 7.4 initialization/applicat ion informat ion ..................................................................................... .....115 7.4.1 introducti on ............................................................................................................. .......115 7.4.2 example #1: external crystal = 32 kh z, bus frequency = 4.19 mhz .........................118 7.4.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz .............................119 7.4.4 example #3: no external crystal c onnection, 5.4 mhz bus frequency .....................121 7.4.5 example #4: internal clock generator trim .................................................................122 7.5 icg registers and c ontrol bits ............................................................................................. ........123 7.5.1 icg control register 1 (icgc1) ...................................................................................124 7.5.2 icg control register 2 (icgc2) ...................................................................................125 7.5.3 icg status register 1 ( icg s1) ............... ................ ............................... .......... 126 7.5.4 icg status register 2 (icgs2) ......................................................................................127 7.5.5 icg filter registers (i cgfltu, icgfltl) .................................................................127 7.5.6 icg trim register (icgtrm) ......................................................................................128 chapter 8 central processor unit (s08cpuv2) 8.1 introducti on ............................................................................................................... ....................129 8.1.1 features ................................................................................................................. .........129 8.2 programmer?s model and cpu registers .....................................................................................13 0 8.2.1 accumulator (a) .......................................................................................................... ..130 8.2.2 index register (h:x) ..................................................................................................... 130 8.2.3 stack pointer (sp) ....................................................................................................... ...131 8.2.4 program counter (pc) ...................................................................................................13 1 8.2.5 condition code register (ccr) ....................................................................................131
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 11 section number title page 8.3 addressing modes ........................................................................................................... ..............133 8.3.1 inherent addressing mode (inh) ..................................................................................133 8.3.2 relative addressing mode (rel) .................................................................................133 8.3.3 immediate addressing mode (imm) .............................................................................133 8.3.4 direct addressing mode (dir) .....................................................................................133 8.3.5 extended addressing mode (ext) ...............................................................................134 8.3.6 indexed addressing mode .............................................................................................134 8.3.6.1 indexed, no offset (ix) ................................................................................134 8.3.6.2 indexed, no offset with post increment (ix+) ............................................134 8.3.6.3 indexed, 8-bit offs et (ix1) ...........................................................................134 8.3.6.4 indexed, 8-bit offset with post increment (ix1+) .......................................134 8.3.6.5 indexed, 16-bit offset (ix2) .........................................................................134 8.3.6.6 sp-relative, 8-bit offset (sp1) ....................................................................134 8.3.6.7 sp-relative, 16-bit offset (sp2) ..................................................................135 8.4 special oper ations ......................................................................................................... ................135 8.4.1 reset seque nce ........................................................................................................... ...135 8.4.2 interrupt sequence ....................................................................................................... ..135 8.4.3 wait mode oper ation ....................................................................................................13 6 8.4.4 stop mode oper ation .....................................................................................................1 36 8.4.5 bgnd instru ction ......................................................................................................... .137 8.5 hcs08 instruction set summary .............................................................................................. ....138 chapter 9 keyboard interrupt (s08kbiv1) 9.1 introducti on ............................................................................................................... ....................149 9.1.1 port a and keyboard interrupt pins ..............................................................................149 9.2 features ................................................................................................................... ......................149 9.2.1 kbi block diag ram .......................................................................................................1 51 9.3 register definition ........................................................................................................ ................151 9.3.1 kbi status and control re gister (kbi1sc) ..................................................................152 9.3.2 kbi pin enable register (kbi1pe) ..............................................................................153 9.4 functional description ..................................................................................................... .............153 9.4.1 pin enables .............................................................................................................. ......153 9.4.2 edge and level se nsitivity ............................................................................................153 9.4.3 kbi interrupt c ontrols ................................................................................................... 154 chapter 10 timer/pwm (s08tpmv1) 10.1 introducti on .............................................................................................................. .....................155 10.2 features .................................................................................................................. .......................155 10.3 tpm block diagram ......................................................................................................... ............157 10.4 pin descriptions .......................................................................................................... ..................158 10.4.1 external tpm cloc k sources ........................................................................................158 10.4.2 tpmxchn ? tpmx channel n i/o pins ......................................................................158 10.5 functional description .................................................................................................... ..............158
mc9s08gb60a data sheet, rev. 2 12 freescale semiconductor section number title page 10.5.1 counter ................................................................................................................. .........159 10.5.2 channel mode se lection ..... ...........................................................................................16 0 10.5.2.1 input capture mode ......................................................................................160 10.5.2.2 output compare mode .................................................................................160 10.5.2.3 edge-aligned pwm mode ...........................................................................160 10.5.3 center-aligned pw m mode ..........................................................................................161 10.6 tpm interrupts ............................................................................................................ ..................163 10.6.1 clearing timer interrupt flags ......................................................................................163 10.6.2 timer overflow interrupt description ...........................................................................163 10.6.3 channel event interrupt description .............................................................................163 10.6.4 pwm end-of-duty-cy cle events ..................................................................................164 10.7 tpm registers and c ontrol bits ............................................................................................ .......164 10.7.1 timer x status and control register (tpmxsc) ...........................................................165 10.7.2 timer x counter registers (tpmxcnth:tpmxcntl) ..............................................166 10.7.3 timer x counter modulo registers (tpmxmodh:tpmxmodl) ..............................167 10.7.4 timer x channel n status and co ntrol register (tpmxcnsc) .....................................168 10.7.5 timer x channel value registers (tpmxcnvh:tpmxcnvl) .....................................169 chapter 11 serial communications interface (s08sciv1) 11.1 introducti on .............................................................................................................. .....................171 11.1.1 features ................................................................................................................ ..........173 11.1.2 modes of op eration ...................................................................................................... .173 11.1.3 block diag ram ........................................................................................................... ....174 11.2 register definition ....................................................................................................... .................176 11.2.1 sci baud rate registers (scixbdh, scixbhl) .........................................................176 11.2.2 sci control register 1 (scixc1) ..................................................................................177 11.2.3 sci control register 2 (scixc2) ..................................................................................178 11.2.4 sci status register 1 (scixs1) .....................................................................................179 11.2.5 sci status register 2 (scixs2) .....................................................................................181 11.2.6 sci control register 3 (scixc3) ..................................................................................181 11.2.7 sci data regist er (scixd) ...........................................................................................182 11.3 functional description .................................................................................................... ..............183 11.3.1 baud rate ge neration .................................................................................................... 183 11.3.2 transmitter functiona l descriptio n ...............................................................................183 11.3.2.1 send break and queued idle ........................................................................184 11.3.3 receiver functional description ...................................................................................184 11.3.3.1 data sampling technique .............................................................................185 11.3.3.2 receiver wakeup operation .........................................................................185 11.3.4 interrupts and st atus flags ............................................................................................. 186 11.3.5 additional sci f unctions ..............................................................................................18 7 11.3.5.1 8- and 9-bit data modes ...............................................................................187 11.3.5.2 stop mode operation ....................................................................................187 11.3.5.3 loop mode ....................................................................................................188
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 13 section number title page 11.3.5.4 single-wire operation ..................................................................................188 chapter 12 serial peripheral interface (s08spiv3) 12.1 introducti on .............................................................................................................. .....................189 12.1.1 features ................................................................................................................ ..........191 12.1.2 block diagra ms .......................................................................................................... ...191 12.1.2.1 spi system block diagram ..........................................................................191 12.1.2.2 spi module block diagram ..........................................................................192 12.1.3 spi baud rate generation .............................................................................................193 12.2 external signal de scription ............................................................................................... ...........194 12.2.1 spsck ? spi serial clock ..........................................................................................194 12.2.2 mosi ? master data out, slave data in .....................................................................194 12.2.3 miso ? master data i n, slave data out .....................................................................194 12.2.4 ss ? slave select .........................................................................................................194 12.3 modes of op eration ........................................................................................................ ...............195 12.3.1 spi in stop modes ....................................................................................................... ..195 12.4 register definition ....................................................................................................... .................195 12.4.1 spi control register 1 (spi1c1) ...................................................................................195 12.4.2 spi control register 2 (spi1c2) ...................................................................................196 12.4.3 spi baud rate register (spi1br) .................................................................................197 12.4.4 spi status register (spi1s) ...........................................................................................19 8 12.4.5 spi data register (spi1d) ............................................................................................199 12.5 functional description .................................................................................................... ..............200 12.5.1 spi clock fo rmats ....................................................................................................... ..200 12.5.2 spi interrupts .......................................................................................................... .......203 12.5.3 mode fault de tection .................................................................................................... 203 chapter 13 inter-integrated circuit (s08iicv1) 13.1 introducti on .............................................................................................................. .....................205 13.1.1 features ................................................................................................................ ..........207 13.1.2 modes of oper ation ...................................................................................................... .207 13.1.3 block diag ram ........................................................................................................... ....208 13.2 external signal de scription ............................................................................................... ...........208 13.2.1 scl ? serial clock line ..............................................................................................208 13.2.2 sda ? serial data line ...............................................................................................208 13.3 register definition ....................................................................................................... .................208 13.3.1 iic address regist er (iic1a) ........................................................................................209 13.3.2 iic frequency divider re gister (iic1f) .......................................................................209 13.3.3 iic control regist er (iic1c) .........................................................................................212
mc9s08gb60a data sheet, rev. 2 14 freescale semiconductor section number title page 13.3.4 iic status register (iic1s) ............................................................................................2 13 13.3.5 iic data i/o regist er (iic1d) .......................................................................................214 13.4 functional description .................................................................................................... ..............215 13.4.1 iic protocol ............................................................................................................ .......215 13.4.1.1 start signal ...............................................................................................216 13.4.1.2 slave address tr ansmission .........................................................................216 13.4.1.3 data transf er .................................................................................................216 13.4.1.4 stop signal ..................................................................................................217 13.4.1.5 repeated start signal ...............................................................................217 13.4.1.6 arbitration pr ocedure ...................................................................................217 13.4.1.7 clock synchroni zation ..................................................................................217 13.4.1.8 handshaking .................................................................................................218 13.4.1.9 clock stretching ............................................................................................218 13.5 resets .................................................................................................................... ........................218 13.6 interrupts ................................................................................................................ .......................218 13.6.1 byte transfer interrupt ................................................................................................. .219 13.6.2 address detect interrupt ................................................................................................ 219 13.6.3 arbitration lost interrupt .............................................................................................. 219 13.7 initialization/applicat ion informat ion .................................................................................... ......220 chapter 14 analog-to-digital converter (s08atdv3) 14.1 introducti on .............................................................................................................. .....................225 14.1.1 features ................................................................................................................ ..........225 14.1.2 modes of oper ation ...................................................................................................... .225 14.1.2.1 stop mode .....................................................................................................225 14.1.2.2 power down mode .......................................................................................225 14.1.3 block diag ram ........................................................................................................... ....225 14.2 signal desc ription ........................................................................................................ .................226 14.2.1 overview ................................................................................................................ ........226 14.2.1.1 channel input pins ? ad1p7?ad1p0 ........................................................227 14.2.1.2 atd reference pins ? v refh , v refl ....................................................................... 227 14.2.1.3 atd supply pins ? v ddad , v ssad ........................................................................... 227 14.3 functional description .................................................................................................... ..............227 14.3.1 mode cont rol ............................................................................................................ .....227 14.3.2 sample and hold ......................................................................................................... ...228 14.3.3 analog input mult iplexer ..............................................................................................23 0 14.3.4 atd module accuracy definitions ...............................................................................230 14.4 resets .................................................................................................................... ........................233 14.5 interrupts ................................................................................................................ .......................233 14.6 atd registers and c ontrol bits ............................................................................................ ........233 14.6.1 atd control (a tdc) ....................................................................................................23 4 14.6.2 atd status and cont rol (atd1sc) ..............................................................................236 14.6.3 atd result data (atd 1rh, atd1rl) ........................................................................237
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 15 section number title page 14.6.4 atd pin enable (atd1pe) ...........................................................................................238 chapter 15 development support 15.1 introducti on .............................................................................................................. .....................239 15.1.1 features ................................................................................................................ ..........240 15.2 background debug contro ller (bdc) ......................................................................................... .240 15.2.1 bkgd pin descri ption ..................................................................................................24 1 15.2.2 communication details .................................................................................................24 2 15.2.3 bdc commands ............................................................................................................ 246 15.2.4 bdc hardware br eakpoint ............................................................................................248 15.3 on-chip debug syst em (dbg) ................................................................................................ ....249 15.3.1 comparators a and b ....................................................................................................2 49 15.3.2 bus capture information and fifo operation ..............................................................249 15.3.3 change-of-flow in formation .........................................................................................250 15.3.4 tag vs. force breakpoint s and triggers ........................................................................250 15.3.5 trigger modes ........................................................................................................... .....251 15.3.6 hardware breakpoints ...................................................................................................2 53 15.4 register definition ....................................................................................................... .................253 15.4.1 bdc registers and control bits ....................................................................................253 15.4.1.1 bdc status and control register (bdcscr) ..............................................254 15.4.1.2 bdc breakpoint match register (bdcbkpt) ............................................255 15.4.2 system background debug force re set register (sbdfr) .........................................255 15.4.3 dbg registers and c ontrol bits ...................................................................................256 15.4.3.1 debug comparator a high register (dbgcah) ........................................256 15.4.3.2 debug comparator a low register (dbgcal) .........................................256 15.4.3.3 debug comparator b high register (dbgcbh) ........................................256 15.4.3.4 debug comparator b low register (dbgcbl) .........................................256 15.4.3.5 debug fifo high regist er (dbgfh) ..........................................................257 15.4.3.6 debug fifo low regist er (dbgfl) ...........................................................257 15.4.3.7 debug control register (dbgc) .................................................................258 15.4.3.8 debug trigger regist er (dbgt) ..................................................................259 15.4.3.9 debug status register (dbgs) ....................................................................260 appendix a electrical characteristics a.1 introducti on ............................................................................................................... ....................261 a.2 absolute maximu m ratings ................................................................................................... .......261 a.3 thermal charac teristic s .................................................................................................... .............262 a.4 electrostatic discharge (esd) protection characte ristics ............................................................263 a.5 dc characteristics ......................................................................................................... ................263
mc9s08gb60a data sheet, rev. 2 16 freescale semiconductor section number title page a.6 supply current char acteristics ............................................................................................. .........267 a.7 atd characteristics ........................................................................................................ ..............271 a.8 internal clock generation m odule characteristics .......................................................................273 a.8.1 icg frequency spec ifications ........................................................................................274 a.9 ac characteristics ......................................................................................................... ................275 a.9.1 control ti ming ........................................................................................................... ....276 a.9.2 timer/pwm (tpm) module timing ..............................................................................277 a.9.3 spi timi ng ............................................................................................................... .......278 a.10 flash specifications ...................................................................................................... .................281 appendix b eb652: migrating from the gb60 series to the gb60a series b.1 overview ................................................................................................................... ....................283 b.2 flash programmin g voltage .................................................................................................. ........283 b.3 flash block protection: 60k devices only ..................................................................................2 83 b.4 internal clock generator: hi gh gain oscillator option ...............................................................283 b.5 internal clock generator: low-powe r oscillator maximum frequency ......................................284 b.6 internal clock generator: loss -of-clock disabl e option ............................................................284 b.7 system device identifi cation register ...................................................................................... ....285 appendix c ordering information an d mechanical drawings c.1 ordering information ....................................................................................................... .............287 c.2 mechanical dr awings ........................................................................................................ ............288
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 17 chapter 1 device overview 1.1 overview the mc9s08gbxxa/gtxxa are members of the low- cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the fam ily use the enhanced hcs08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 features features have been organized to reflect: ? standard features of the hcs08 family ? features of the mc9s08gbxxa/gtxxa mcu 1.2.1 standard features of the hcs08 family ? 40-mhz hcs08 cpu (central processor unit) ? hc08 instruction set with added bgnd instruction ? background debugging system (see also chapter 15, ?development support ?) ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) ? debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data . debug module supports both tag and force breakpoints. ? support for up to 32 interrupt/reset sources ? power-saving modes: wait plus three stops ? system protection features: ? optional computer opera ting properly (cop) reset ? low-voltage detection with reset or interrupt ? illegal opcode detection with reset ? illegal address detection with reset (som e devices don?t have illegal addresses)
chapter 1 device overview mc9s08gb60a data sheet, rev. 2 18 freescale semiconductor 1.2.2 features of mc9s08gbxxa/gtxxa series of mcus ? on-chip in-circuit pr ogrammable flash memory: ? fully read/write func tional across voltage and temperature ranges ? block protection and security options ? (see table 1-1 for device-specific information) ? on-chip random-access memory (ram) (see table 1-1 for device specific information) ? 8-channel, 10-bit analog-t o-digital converter (atd) ? two serial communications interface modules (sci) ? serial peripheral interface module (spi) ? multiple clock source options: ? internally generated clock with 0.2% trimming resolution and 0.5% deviation across voltage ?crystal ? resonator ? external clock ? inter-integrated circuit bus module to operate up to 100 kbps (iic) ? one 3-channel and one 5-cha nnel 16-bit timer/pulse width m odulator (tpm) modules with selectable input capture, output compare, and edge-ali gned pwm capability on ea ch channel. each timer module may be configured for buffered, ce ntered pwm (cpwm) on all channels (tpmx). ? 8-pin keyboard inte rrupt module (kbi) ? 16 high-current pins (lim ited by package dissipation) ? software selectable pullups on ports when used as input. selection is on an individual port bit basis. during output mode, pul lups are disengaged. ? internal pullup on reset and irq pin to reduce customer system cost ? up to 56 general-purpose input/output (i/o) pins, depending on package selection ? 64-pin low-profile quad flat package (lqfp) ? mc9s08gbxxa ? 48-pin quad flat package, no lead (qfn) ? mc9s08gtxxa ? 44-pin quad flat package (qfp) ? mc9s08gtxxa ? 42-pin s kinny dual in-line package (sdip) ? mc9s08gtxxa
chapter 1 device overview mc9s08gb60a data sheet, rev. 2 freescale semiconductor 19 1.2.3 devices in the mc9s08gbxxa/gtxxa series table 1-1 lists the devices available in the mc9s08gbxxa/gtxxa seri es and summarizes the differences among them. 1.3 mcu block diagrams these block diagrams show the struct ure of the mc9s08 gbxxa/gtxxa mcus. table 1-1. devices in the mc9s08gbxxa/gtxxa series device flash ram tpm i/o packages mc9s08gb60a 60k 4k one 3-channel and one 5-channel, 16-bit timer 56 64 lqfp mc9s08gb32a 32k 2k one 3-channel and one 5-channel, 16-bit timer 56 64 lqfp mc9s08gt60a 60k 4k two 2-channel, 16-bit timers 39 36 33 48 qfn 1 44 qfp 42 sdip 1 the 48-pin qfn package has one 3-channel and one 2-channel 16-bit tpm. mc9s08gt32a 32k 2k two 2-channel, 16-bit timers 39 36 33 48 qfn (1) 44 qfp 42 sdip
chapter 1 device overview mc9s08gb60a data sheet, rev. 2 20 freescale semiconductor figure 1-1. mc9s08gbxxa/gtxxa block diagram ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see ta bl e 2 - 2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key: irq
chapter 1 device overview mc9s08gb60a data sheet, rev. 2 freescale semiconductor 21 table 1-2 lists the functional versions of the on-chip modules. 1.4 system clock distribution figure 1-2. system clock distribution diagram some of the modules inside the mcu have clock source choices. figure 1-2 shows a simplified clock connection diagram. the icg supplies the clock sources: ? icgout is an output of the icg module. it is one of the following: ? the external crystal oscillator ? an external clock source ? the output of the digitally-controlled osci llator (dco) in the frequency-locked loop sub-module control bits inside the icg dete rmine which source is connected. table 1-2. block versions module version analog-to-digital converter (atd) 3 internal clock generator (icg) 2 inter-integrated circuit (iic) 1 keyboard interrupt (kbi) 1 serial communications interface (sci) 1 serial peripheral interface (spi) 3 timer pulse-width modulator (tpm) 1 central processing unit (cpu) 2 atd has min and max frequency requirements. see chapter 1, ?device overview ? and appendix a, ?electrical characteristics . flash has frequency requirements for program and erase operation. see appendix a, ?electrical characteristics . * icglclk is the alternate bdc clock source for the mc9s08gbxxa/gtxxa. tpm1 tpm2 iic1 sci1 sci2 spi1 bdc cpu atd1 ram flash icg icgout 2 ffe system logic busclk icglclk* control fixed freq clock (xclk) icgerclk rti 2
chapter 1 device overview mc9s08gb60a data sheet, rev. 2 22 freescale semiconductor ? ffe is a control signal generated inside the icg. if the frequency of icgout > 4 the frequency of icgerclk, this signal is a logic 1 and the fixed-frequency clock will be the icgerclk. otherwise the fixed-frequenc y clock will be busclk. ? icglclk ? development tools can select this internal self-clocked source (~ 8 mhz) to speed up bdc communications in systems where the bus clock is slow. ? icgerclk ? external reference clock can be sele cted as the real-time interrupt clock source.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 23 chapter 2 pins and connections 2.1 introduction this section describes signals that connect to package pins. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals.
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 24 freescale semiconductor 2.2 device pin assignment figure 2-1. mc9s08gbxxa in 64-pin lqfp package ptc3/scl1 1 2 3 4 5 6 7 8 ptc0/txd2 ptc1/rxd2 ptc4 ptc5 ptc6 ptc7 ptd0/tpm1ch0 v dd v ss pte7 pte6 pte5/spsck1 pte4/mosi1 v refh v refl ptf5 ptf6 ptf7 ptb2/ad1p2 ptb7/ad1p7 pta5/kbi1p5 ptf0 ptg6 v ssad v ddad ptf1 pta2/kbi1p2 pta6/kbi1p6 pta7/kbi1p7 43 42 41 40 39 38 18 19 20 21 22 23 505152535455 17 32 33 49 48 64 9 ptf2 10 ptf3 11 ptf4 16 irq ptd1/tpm1ch1 24 ptd2/tpm1ch2 25 ptd3/tpm2ch0 26 ptd4/tpm2ch1 27 ptb6/ad1p6 37 ptb5/ad1p5 36 ptb4/ad1p4 35 ptb3/ad1p3 34 ptg0/bkgd/ms 56 ptg1/xtal 57 ptg2/extal 58 ptg3 59 ptc2/sda1 12 pte0/txd1 13 14 15 pte1/rxd1 ptd5/tpm2ch2 28 29 30 31 pta0/kbi1p0 44 45 46 pta1/kbi1p1 47 ptg5 63 62 61 ptg4 60 reset ptg7 pte2/ss 1 pte3/miso1 ptd6/tpm2ch3 ptd7/tpm2ch4 ptb1/ad1p1 ptb0/ad1p0 pta4/kbi1p4 pta3/kbi1p3
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 freescale semiconductor 25 figure 2-2. mc9s08gtxxa in 48-pin qfn package 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 36 33 32 31 30 29 28 27 26 13 reset pte0/txd1 pte1/rxd1 irq ptc0/txd2 ptc1/rxd2 ptc2/sda1 ptc3/scl1 ptc4 ptc5 ptc6 ptd1/tpm1ch1 ptd0/tpm1ch0 v dd v ss1 pte5/spsck1 pte4/mosi1 pte3/miso1 pte2/ss 1 ptd3/tpm2ch0 ptd4/tpm2ch1 ptb0/ad1p0 ptb6/ad1p6 ptb7/ad1p7 v refh v refl pta0/kbi1p0 ptb2/ad1p2 ptb3/ad1p3 ptb1/ad1p1 ptb4/ad1p4 ptb5/ad1p5 pta4/kbi1p4 pta5/kbi1p5 v ddad ptg2/extal ptg1/xtal ptg0/bkgd/ms v ssad pta1/kbi1p1 pta6/kbi1p6 pta7/kbi1p7 pta3/kbi1p3 pta2/kbi1p2 24 23 25 35 34 37 38 12 ptc7 v ss2 ptd2/tpm1ch2 ptg3
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 26 freescale semiconductor figure 2-3. mc9s08gtxxa in 44-pin qfp package 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 12 23 reset pte0/txd1 pte1/rxd1 irq ptc0/txd2 ptc1/rxd2 ptc2/sda1 ptc3/scl1 ptc4 ptc5 ptc6 ptd1/tpm1ch1 ptd0/tpm1ch0 v dd v ss pte5/spsck1 pte4/mosi1 pte3/miso1 pte2/ss 1 ptd3/tpm2ch0 ptd4/tpm2ch1 ptb0/ad1p0 ptb6/ad1p6 ptb7/ad1p7 v refh v refl pta0/kbi1p0 ptb2/ad1p2 ptb3/ad1p3 ptb1/ad1p1 ptb4/ad1p4 ptb5/ad1p5 pta4/kbi1p4 pta5/kbi1p5 v ddad ptg2/extal ptg1/xtal ptg0/bkgd/ms v ssad pta1/kbi1p1 pta6/kbi1p6 pta7/kbi1p7 pta3/kbi1p3 pta2/kbi1p2
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 freescale semiconductor 27 figure 2-4. . mc9s08gtxxa in 42-pin sdip package 2.3 recommended system connections figure 2-4 shows pin connections that are common to al most all mc9s08gbxxa application systems. mc9s08gtxxa connections wi ll be similar except for the number of i/ o pins available. a more detailed discussion of system connections follows. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 irq pte1/rxd1 pte0/txd1 v ddad ptc2/sda1 ptc3/scl1 ptc4 ptb5/ad1p5 ptb6/ad1p6 ptb7/ad1p7 v refh v refl pta0/kbi1p0 pta1/kbi1p1 pta2/kbi1p2 pta4/kbi1p4 pta3/kbi1p3 ptb4/ad1p4 pta5/kbi1p5 pta6/kbi1p6 pta7/kbi1p7 v ssad ptg0/bkgd/ms ptg1/xtal ptg2/extal reset ptc0/txd2 ptc1/rxd2 15 28 pte2/ss 1 ptb3/ad1p3 16 27 pte3/miso1 ptb2/ad1p2 17 26 pte4/mosi1 ptb1/ad1p1 18 25 pte5/spsck1 ptb0/ad1p0 19 24 v ss ptd4/tpm2ch1 20 23 v dd ptd3/tpm2ch0 21 22 ptd0/tpm1ch0 ptd1/tpm1ch1
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 28 freescale semiconductor figure 2-5. basic system connections v dd v dd v ss xtal extal bkgd/ms reset optional manual reset port a v dd background header c2 c1 x1 r f r s c by 0.1 f c blk 10 f + 3 v + system power i/o and peripheral interface to system application pta0/kbi1p0 pta1/kbi1p1 pta2/kbi1p2 pta3/kbi1p3 pta4/kbi1p4 pta5/kbi1p5 pta6/kbi1p6 pta7/kbi1p7 v dd port b ptb0/ad1p0 ptb1/ad1p1 ptb2/ad1p2 ptb3/ad1p3 ptb4/ad1p4 ptb5/ad1p5 ptb6/ad1p6 ptb7/ad1p7 port c ptc0/txd2 ptc1/rxd2 ptc2/sda1 ptc3/scl1 ptc4 ptc5 ptc6 ptc7 port d ptd0/tpm1ch0 ptd1/tpm1ch1 ptd2/tpm1ch2 ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptd7/tpm2ch4 port e pte0/txd1 pte1/rxd1 pte2/ss1 pte3/miso1 pte4/mosi1 pte5/spsck1 pte6 pte7 port g ptg0/bkdg/ms ptg1/xtal ptg2/extal ptg3 ptg4 ptg5 ptg6 ptg7 port f ptf0 ptf1 ptf2 ptf3 ptf4 ptf5 ptf6 ptf7 irq asynchronous interrupt input notes: 1. not required if using the internal oscillator option. 2. these are the same pins as ptg1 and ptg2. 3. bkgd/ms is the same pin as ptg0. 4. the 48-pin qfn has 2 v ss pins (v ss1 and v ss2 ), both of which must be connected to gnd. 5. rc filters on reset and irq are recommended for emc-sensitive applications note 1 note 2 note 2 note 3 mc9s08gbxxa/gtxxa v ddad v ssad c byad 0.1 f v refl v refh note 4 v dd 4.7 k ?10 k 0.1 f 4.7 k ?10 k 0.1 f note 5 note 5
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 freescale semiconductor 29 2.3.1 power v dd and v ss are the primary power supply pi ns for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an internal voltage regulator. the intern al voltage regulator provides regulated lower-voltage source to the cpu and ot her internal circuitry of the mcu. typically, application systems have two separate capac itors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as close to the mcu power pins as practical to suppress high-frequency noise. v ddad and v ssad are the analog power supply pi ns for the mcu. this volta ge source supplies power to the atd. a 0.1- f ceramic bypass capacitor should be located as close to the mcu power pins as practical to suppress high-frequency noise. 2.3.2 oscillator out of reset, the mcu uses an internally generated clock (self-clocked mode ? f self_reset ), that is approximately equivalent to an 8-mhz crystal rate. this frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long cr ystal startup delay. this mcu also contains a trimmable intern al clock generator (icg ) module that can be used to run the mcu. for more information on the icg, see chapter 7, ?internal cloc k generator (s08icgv2) .? the oscillator in this mcu is a pierce oscillator th at can accommodate a crysta l or ceramic resonator in either of two frequency ranges selected by the range bi t in the icgc1 register. rather than a crystal or ceramic resonator, an external os cillator can be connected to the extal input pin, and the xtal output pin can be used as general i/o. refer to figure 2-4 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resi stors, and some metal film resistors, have too much inductance. c1 and c2 nor mally should be high-qual ity ceramic capacitors that are specifically designed for high-freque ncy applications. r f is used to provide a bias path to keep the extal input in its linear range during crysta l startup and its value is not generally crit ical. typical systems use 1 m to 10 m . higher values are sensitive to humidity and lower values re duce gain and (in extreme ca ses) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a specific crystal or resonator. be sure to take into acc ount printed circuit board (p cb) capacitance and mcu pin capacitance when sizing c1 and c2. the crystal manufacturer typical ly specifies a load capacitance which is the series combination of c1 and c2 which are usually the same size. as a first-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal). 2.3.3 reset reset is a dedicated pin with a pullup device built in. it has input hyste resis, a high current output driver, and no output slew rate control. internal power-on reset a nd low-voltage reset circ uitry typically make external reset circuitry unnecessary . this pin is normally connected to the standard 6-pin background
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 30 freescale semiconductor debug connector so a development syst em can directly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any reset is initiated (wheth er from an external signal or from an internal system), the reset pin is driven low for approximately 34 cycles of f self_reset , released, and sampled again approximately 38 cycles of f self_reset later. if reset was caused by an internal source such as low-vol tage reset or watchdog timeout, the circuitry expect s the reset pin sample to return a logi c 1. the reset circuitr y decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (srs). in emc-sensitive applications, an external rc filter is r ecommended on the reset pin. see figure 2-4 for an example. 2.3.4 background / mode select (ptg0/bkgd/ms) the background/mode select (bkgd/ms) shares its function with an i/o port pin. while in reset, the pin functions as a mode select pin. im mediately after reset rises the pin functions as the background pin and can be used for background debug communication. whil e functioning as a bac kground/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. when used as an i/o port (ptg0) the pin is limited to output only. if nothing is connected to this pi n, the mcu will enter normal operating m ode at the rising edge of reset. if a debug system is connected to the 6-pin standard background de bug header, it can hold bkgd/ms low during the rising edge of reset which fo rces the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communi cations using a custom protocol that uses 16 clock cycles of the target mcu?s bdc clock per bit time. the target mcu?s bdc clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the bkgd/ms pin that could interfer e with background serial communications. although the bkgd pin is a ps eudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute valu e of the internal pullup devi ce play almost no role in determining rise and fall times on the bkgd pin. 2.3.5 general-purpose i/o and peripheral ports the remaining 55 pins are shared among general-purpos e i/o and on-chip peripheral functions such as timers and serial i/o syst ems. (17 of these pins are not bonded out on the 48-pin package, 20 of these pins are not bonded out on the 44- pin package and 22 of hese pins are not bonded out on the 42-pin package.) immediately after reset, al l 55 of these pins are configured as high-impedance genera l-purpose inputs with internal pullup devices disabled. note to prevent extra current drain fr om floating input pins, the reset initialization routine in the appli cation program should either enable on-chip pullup devices or change the di rection of unused pi ns to outputs so the pins do not float.
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 freescale semiconductor 31 for information about controlling these pins as general-purpose i/o pins, see chapter 6, ?parallel input/output .? for information about how and when on-chip peripheral systems use these pins, refer to the appropriate section from table 2-1 . when an on-chip peripheral system is controlling a pin, data direction c ontrol bits still determine what is read from port data registers even though the periphe ral module controls the pi n direction by controlling the enable for the pin?s output buffer. see chapter 6, ?parallel input/output ? for details. pullup enable bits for each input pin control whether on-ch ip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. when the pta7?pta4 pins are controlled by the kbi modul e and are configured for rising-edge /high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. si milarly, when irq is configured as the irq input and is set to dete ct rising edges, the pullup enable c ontrol bit enables a pulldown device rather than a pullup device. table 2-1. pin sharing references port pins alternate function reference 1 1 see this section for information about modules that share these pins. pta7?pta0 kbi1p7?kbi1p0 chapter 2, ?pins and connections? ptb7?ptb0 ad1p7?ad1p0 chapter 14, ?analog-to-digital converter (s08atdv3)? ptc7?ptc4 ? chapter 6, ?parallel input/output? ptc3?ptc2 scl1?sda1 chapter 13, ?inter-integra ted circuit (s08iicv1)? ptc1?ptc0 rxd2?txd2 chapter 11, ?serial communications interface (s08sciv1)? ptd7?ptd3 tpm2ch4? tpm2ch0 chapter 10, ?timer/p wm (s08tpmv1)? ptd2?ptd0 tpm1ch2? tpm1ch0 chapter 10, ?timer/p wm (s08tpmv1)? pte7?pte6 ? chapter 6, ?parallel input/output? pte5 pte4 pte3 pte2 spsck1 miso1 mosi1 ss 1 chapter 12, ?serial peripheral interface (s08spiv3)? pte1?pte0 rxd1?txd1 chapter 11, ?serial communications interface (s08sciv1)? ptf7?ptf0 ? chapter 6, ?parallel input/output? ptg7?ptg3 ? chapter 6, ?parallel input/output? ptg2?ptg1 extal?xtal chapter 7, ?internal clock generator (s08icgv2)? ptg0 bkgd/ms chapter 15, ?development support?
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 32 freescale semiconductor 2.3.6 signal properties summary table 2-2 summarizes i/o pin characteristics. these ch aracteristics are determined by the way the common pin interfaces are hard wired to internal circuits. table 2-2. signal properties pin name dir high current pin output slew 1 pull-up 2 comments v dd ??? v ss ??? the 48-pin qfn package has two v ss pins ? v ss1 and v ss2 . v ddad ??? v ssad ??? v refh ??? v refl ??? reset i/o y n y pin contains integrated pullup. irq i? ? y irqpe must be set to enable irq function. irq does not have a clamp diode to v dd . irq should not be driven above v dd . pullup/pulldown active when irq pin function enabled. pullup forced on when irq enabled for falling edges; pulldown forced on when irq enabled for rising edges. pta0/kbi1p0 i/o n swc swc pta1/kbi1p1 i/o n swc swc pta2/kbi1p2 i/o n swc swc pta3/kbi1p3 i/o n swc swc pta4/kbi1p4 i/o n swc swc pullup/pulldown active when kbi pin function enabled. pullup forced on when kbi1px enabled for falling edges; pulldown forced on when kbi1px enabled for rising edges. pta5/kbi1p5 i/o n swc swc pta6/kbi1p6 i/o n swc swc pta7/kbi1p7 i/o n swc swc ptb0/ad1p0 i/o n swc swc ptb1/ad1p1 i/o n swc swc ptb2/ad1p2 i/o n swc swc ptb3/ad1p3 i/o n swc swc ptb4/ad1p4 i/o n swc swc ptb5/ad1p5 i/o n swc swc ptb6/ad1p6 i/o n swc swc ptb7/ad1p7 i/o n swc swc ptc0/txd2 i/o y swc swc when pin is configured for sci function, pin is configured for partial output drive. ptc1/rxd2 i/o y swc swc ptc2/sda1 i/o y swc swc ptc3/scl1 i/o y swc swc ptc4 i/o y swc swc ptc5 i/o y swc swc not available on 42-pin package ptc6 i/o y swc swc not available on 42-pin package
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 freescale semiconductor 33 ptc7 i/o y swc swc not available on 42-pin package ptd0/tpm1ch0 i/o n swc swc ptd1/tpm1ch1 i/o n swc swc ptd2/tpm1ch2 i/o n swc swc not available on 42-pin , or 44-pin package ptd3/tpm2ch0 i/o n swc swc ptd4/tpm2ch1 i/o n swc swc ptd5/tpm2ch2 i/o n swc swc not available on 42-, 44-, or 48-pin package ptd6/tpm2ch3 i/o n swc swc not available on 42-, 44-, or 48-pin package ptd7/tpm2ch4 i/o n swc swc not available on 42-, 44-, or 48-pin package pte0/txd1 i/o n swc swc pte1/rxd1 i/o n swc swc pte2/ss 1 i/o n swc swc pte3/miso1 i/o n swc swc pte4/mosi1 i/o n swc swc pte5/spsck1 i/o n swc swc pte6 i/o n swc swc not available on 42-, 44-, or 48-pin package pte7 i/o n swc swc not available on 42-, 44-, or 48-pin package ptf0 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf1 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf2 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf3 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf4 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf5 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf6 i/o y swc swc not available on 42-, 44-, or 48-pin package ptf7 i/o y swc swc not available on 42-, 44-, or 48-pin package ptg0/bkgd/ms o n swc swc pullup enabled and slew rate disabled when bdm function enabled. ptg1/xtal i/o n swc swc pullup and slew rate disabled when xtal pin function. ptg2/extal i/o n swc swc pullup and slew rate disabled when extal pin function. ptg3 i/o n swc swc not available on 42- or 44-pin package ptg4 i/o n swc swc not available on 42-, 44-, or 48-pin package ptg5 i/o n swc swc not available on 42-, 44-, or 48-pin package ptg6 i/o n swc swc not available on 42-, 44-, or 48-pin package ptg7 i/o n swc swc not available on 42-, 44-, or 48-pin package 1 swc is software controlled slew rate, the regi ster is associated with the respective port. 2 swc is software controlled pullup resistor, the r egister is associated with the respective port. table 2-2. signal properties (continued) pin name dir high current pin output slew 1 pull-up 2 comments
chapter 2 pins and connections mc9s08gb60a data sheet, rev. 2 34 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 35 chapter 3 modes of operation 3.1 introduction the operating modes of the mc9s08gb xxa/gtxxa are described in this section. entry into each mode, exit from each mode, and func tionality while in each of the modes are described. 3.2 features ? active background mode for code development ? wait mode: ? cpu shuts down to conserve power ? system clocks running ? full voltage regulation maintained ? stop modes: ? system clocks stopped; vol tage regulator in standby ? stop1 ? full power down of internal circuits for maximum power savings ? stop2 ? partial power down of intern al circuits, ram contents retained ? stop3 ? all internal circuits powered for fast recovery 3.3 run mode this is the normal operating mode for the mc9s08g bxxa/gtxxa. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode , the cpu executes code from internal memory with execution beginning at the address fe tched from memory at 0xfffe:0xffff after reset. 3.4 active background mode the active background mode functions are manage d through the background de bug controller (bdc) in the hcs08 core. the bdc, together with the on-chip debug module (dbg), provide the means for analyzing mcu operation duri ng software development. active background mode is entered in any of five ways: ? when the bkgd/ms pin is low at the rising edge of reset ? when a background command is received through the bkgd pin ? when a bgnd instruction is executed ? when encountering a bdc breakpoint
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 36 freescale semiconductor ? when encountering a dbg breakpoint after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructi ons from the user?s application program. background commands are of two types: ? non-intrusive commands, defined as commands that can be issu ed while the user program is running. non-intrusive commands can be issued through the bkgd pin while the mcu is in run mode; non-intrusive commands can also be executed while the mcu is in the active background mode. non-intrusive commands include: ? memory access commands ? memory-access-with-status commands ? bdc register access commands ? the background command ? active background commands, which can be execute d only while the mcu is in active background mode. active background commands include commands to: ? read or write cpu registers ? trace one user program instruction at a time ? leave active background mode to return to the user?s application program (go) the active background mode is used to program a bootloader or user a pplication program into the flash program memory before the mcu is operated in run mode for the first time. when the mc9s08gbxxa/gtxxa is shipped from the freescale semiconductor fact ory, the flash program memory is erased by default unless specifical ly noted so there is no program th at could be executed in run mode until the flash memory is initially programmed. the activ e background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about th e active background mode, refer to chapter 15, ?development support . 3.5 wait mode wait mode is entered by executing a wait instruction. u pon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking opera tions leading to the in terrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background co mmand and memory-access-with-s tatus commands are available when the mcu is in wait mode. the memory-access- with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 3.6 stop modes one of three stop modes is entere d upon execution of a stop instruct ion when the stope bit in the system option register is se t. in all stop modes, all internal clocks are halted. if the stope bit is not set
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 freescale semiconductor 37 when the cpu executes a stop instruction, the mcu w ill not enter any of the stop modes and an illegal opcode reset is forced. the stop modes are selected by setting the appropriate bits in spmsc2. table 3-1 summarizes the behavior of th e mcu in each of the stop modes. 3.6.1 stop1 mode the stop1 mode provides the lowest possible standby power c onsumption by causing the internal circuitry of the mcu to be powered down. stop1 can be entered only if the lvd circ uit is not enabled in stop modes (either lvde or lvdse not set). when the mcu is in stop1 mode, all internal circuits th at are powered from the vol tage regulator are turned off. the voltage regulator is in a low- power standby state, as is the atd. exit from stop1 is performed by asserting either of the wake-up pins on the mcu: reset or irq. irq is always an active low input when th e mcu is in stop1, regard less of how it was conf igured before entering stop1. entering stop1 mode automatically assert s lvd. stop1 cannot be exited until v dd > v lvdh/l rising (v dd must rise above the lvi rearm voltage). upon wake-up from stop1 mode, the mcu will start up as from a power-on rese t (por). the cpu will take the reset vector. 3.6.2 stop2 mode the stop2 mode provides very low standby power consumption and maintains the contents of ram and the current state of all of the i/o pins. stop2 can be entered only if the lvd circuit is not enabled in stop modes (either lvde or lvdse not set). before entering stop2 mode, the user must save the contents of the i/o port registers, as well as any other memory-mapped registers they want to restore after exit of stop2, to locations in ram. upon exit of stop2, these values can be restored by user software before pin latches are opened. when the mcu is in stop2 mode, all internal circuits th at are powered from the vol tage regulator are turned off, except for the ram. the voltage regulator is in a low-power standby state, as is the atd. upon entry table 3-1. stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti stop1 1 0 off off off disabled 1 1 either atd stop mode or power-down mode depending on the state of atdpu. off reset off stop2 1 1 off standby off disabled standby states held optionally on stop3 0 don?t care standby standby off 2 2 crystal oscillator can be configured to r un in stop3. please see the icg registers. disabled standby states held optionally on
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 38 freescale semiconductor into stop2, the states of the i/o pins are latched. the st ates are held while in st op2 mode and after exiting stop2 mode until a 1 is writ ten to ppdack in spmsc2. exit from stop2 is performed by asserting either of the wake-up pins: reset or irq, or by an rti interrupt. irq is always an active low input when th e mcu is in stop2, regardless of how it was configured before entering stop2. upon wake-up from stop2 mode, the mcu will start up as from a power-on reset (por) except pin states remain latched. the cpu will take the reset vector. the system and all peripherals will be in their default reset states and must be initialized. after waking up from stop2, the ppdf bit in spmsc2 is set. this flag may be used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latc hed until a 1 is written to ppdack in spmsc2. to maintain i/o state for pins that were configured as general-purpose i/o, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the register bits will assume their rese t states when the i/o pin latches are opened and the i/o pins will switch to their reset states. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.3 stop3 mode upon entering the stop3 mode, all of the clocks in the mcu, including the oscillator itself, are halted. the icg is turned off, the atd is disabl ed, and the voltage regulator is put in standby. the states of all of the internal registers and logic, as well as the ram content, ar e maintained. the i/o pin states are not latched at the pin as in stop2. instead they are maintained by vi rtue of the states of the internal logic driving the pins being maintained. exit from stop3 is perf ormed by asserting reset , an asynchronous interrupt pi n, or through the real-time interrupt. the asynchronous interrupt pins are the irq or kbi pins. if stop3 is exited by means of the reset pin, then the mcu will be rese t and operation will resume after taking the reset vector. exit by means of an asynchronous interrupt or the real-time interrupt will result in the mcu taking the appropriate interrupt vector. a separate self-clocked source ( 1 khz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. when rtis2:rt is1:rtis0 = 0:0:0, the real -time interrupt function and this 1-khz source are disabled. po wer consumption is lower when the 1-khz source is disabled, but in that case the real-time interrupt cannot wake the mcu from stop.
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 freescale semiconductor 39 3.6.4 active bdm enabled in stop mode entry into the active bac kground mode from run mode is enabled if the enbdm bit in bdcscr is set. this register is described in the chapter 15, ?development support ,? section of this data sheet. if enbdm is set when the cpu executes a stop instruction, th e system clocks to the background debug logic remain active when the mcu enters stop mode so backgr ound debug communication is still possible. in addition, the voltage regulator does not enter its low-power sta ndby state but maintains full internal regulation. if the user attempts to enter either stop1 or stop2 wi th enbdm set, the mcu will instead enter stop3. most background commands are not available in stop mode. the memo ry-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. af ter the device enters background debug mode, all background commands are available. the table below summari zes the behavior of the mcu in stop when entry into the background debug mode is enabled. 3.6.5 lvd enabled in stop mode the lvd system is capable of genera ting either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enabled in stop by setting the lvde and the lvdse bits in spmsc1 when the cpu executes a stop instruction, then the voltage regulator remains activ e during stop mode. if the user attempts to enter either stop1 or stop2 with the lvd enabled for stop (lvdse = 1), the mcu will instead enter stop3. the table below summarizes the behavior of the mcu in stop when the lvd is enabled. 3.6.6 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal periphera l modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, table 3-2. bdm enabled stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti 1 1 the 1 khz internal rti clock is not available in stop3 with active bdm enabled. stop3 don?t care don?t care standby standby active disabled 2 2 either atd stop mode or power-down mode depending on the state of atdpu. active states held optionally on table 3-3. lvd enabled stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti stop3 don?t care don?t care standby standby standby disabled 1 1 either atd stop mode or power-down mode depending on the state of atdpu. active states held optionally on
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 40 freescale semiconductor clocks to the peripheral systems are halte d to reduce power consumption. refer to section 3.6.1, ?stop1 mode ,? section 3.6.2, ?stop2 mode ,? and section 3.6.3, ?stop3 mode ,? for specific information on system behavior in stop modes. i/o pins ? all i/o pin states remain unchange d when the mcu enters stop3 mode. ? if the mcu is configured to go into stop2 mode, all i/o pins states are latched before entering stop. ? if the mcu is configured to go into stop1 mode, all i/o pins are forced to their default reset state upon entry into stop. memory ? all ram and register contents are preserved while the mcu is in stop3 mode. ? all registers will be reset up on wake-up from stop2, but the contents of ram are preserved and pin states remain latched until the ppdack bit is written. the user may save any memory-mapped register data into ram before entering sto p2 and restore the data upon exit from stop2. ? all registers will be reset up on wake-up from stop1 and the cont ents of ram are not preserved. the mcu must be initialized as upon reset. the contents of th e flash memory are nonvolatile and are preserved in any of the stop modes. icg ? in stop3 mode, the icg enters its low-power standby state. either the oscillator or the internal reference may be kept running when the icg is in standby by setting the appropriate control bit. in both stop2 and stop1 modes, the icg is turned off. neither the oscillator nor the internal refe rence can be kept running in stop2 or stop1, even if enabled within the icg module. tpm ? when the mcu enters stop mode, the clock to the tpm1 and tpm2 modules stop. the modules halt operation. if the mcu is configured to go into stop2 or stop1 mode, the tpm modules will be reset upon wake-up from stop and must be reinitialized. atd ? when the mcu enters st op mode, the atd will ente r a low-power standby state . no conversion operation will occur while in stop. if the mcu is configured to go into stop2 or stop1 mode, the atd will be reset upon wake-up from stop and must be reinitialized. kbi ? during stop3, the kbi pins that are enabled cont inue to function as inte rrupt sources that are capable of waking the mcu from stop3. the kbi is disabled in stop1 a nd stop2 and must be reinitialized after waking up from ei ther of these modes. rti ? during stop2 and stop3, the rti continues to operate as an interrupt wakeup source. during stop1, the rti is disabled. in stop2, the rti uses the intern al 1 khz rti clock, but in stop3 mode, the rti uses either the external clock or the internal rti cl ock. when the active bdm m ode is enabled though, the internal rti clock is not operational. sci ? when the mcu enters stop mode, the clocks to the sci1 and sci2 modules stop. the modules halt operation. if the mcu is configured to go into stop2 or stop1 mode, the sci modules will be reset upon wake-up from stop and must be reinitialized. spi ? when the mcu enters stop m ode, the clocks to the spi modul e stop. the module halts operation. if the mcu is configured to go in to stop2 or stop1 mode, the spi module will be reset up on wake-up from stop and must be reinitialized.
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 freescale semiconductor 41 iic ? when the mcu enters stop mo de, the clocks to the iic module stops. the modul e halts operation. if the mcu is configured to go into stop2 or stop1 mode, the iic modu le will be rese t upon wake-up from stop and must be reinitialized. voltage regulator ? the voltage regulat or enters a low-power standby state when the mcu enters any of the stop modes unless the lvd is enab led in stop mode or bdm is enabled.
chapter 3 modes of operation mc9s08gb60a data sheet, rev. 2 42 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 43 chapter 4 memory 4.1 mc9s08gbxxa/gtxxa memory map as shown in figure 4-1 , on-chip memory in the mc9s08gbxxa/gtxxa series of mcus consists of ram, flash program memory for nonvol atile data storage, plus i/o a nd control/status registers. the registers are divided into three groups: ? direct-page registers (0x0000 through 0x007f) ? high-page registers (0x1800 through 0x182b) ? nonvolatile registers (0xffb0 through 0xffbf) figure 4-1. mc9s08gbxxa/gtxxa memory map direct page registers ram flash high page registers flash 4096 bytes 1920 bytes 59348 bytes 0x0000 0x007f 0x0080 0x107f 0x1800 0x17ff 0x182b 0x182c 0xffff 0x1080 direct page registers ram high page registers flash 32768 bytes 0x0000 0x007f 0x0080 0x087f 0x1800 0x17ff 0x182b 0x182c 0xffff 0x0880 2048 bytes unimplemented 26580 bytes unimplemented 3968 bytes 0x8000 0x7fff mc9s08gb60a/mc9s08gt60a mc9s08gb32a/mc9s08gt32a
chapter 4 memory mc9s08gb60a data sheet, rev. 2 44 freescale semiconductor 4.1.1 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. the vector name s shown in this table are the labels used in the freescale-provided equate file for the mc 9s08gbxxa/gtxxa. for more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to chapter 5, ?resets, interrupts, and system configuration .? table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:ffc1 0xffca:ffcb unused vector space (available for user program) 0xffcc:ffcd rti vrti 0xffce:ffcf iic viic1 0xffd0:ffd1 atd conversion vatd1 0xffd2:ffd3 keyboard vkeyboard1 0xffd4:ffd5 sci2 tr ansmit vsci2tx 0xffd6:ffd7 sci2 receive vsci2rx 0xffd8:ffd9 sci2 error vsci2err 0xffda:ffdb sci1 transmit vsci1tx 0xffdc:ffdd sci1 receive vsci1rx 0xffde:ffdf sci1 error vsci1err 0xffe0:ffe1 spi vspi1 0xffe2:ffe3 tpm2 overflow vtpm2ovf 0xffe4:ffe5 tpm2 channel 4 vtpm2ch4 0xffe6:ffe7 tpm2 channel 3 vtpm2ch3 0xffe8:ffe9 tpm2 channel 2 vtpm2ch2 0xffea:ffeb tpm2 channel 1 vtpm2ch1 0xffec:ffed tpm2 channel 0 vtpm2ch0 0xffee:ffef tpm1 overflow vtpm1ovf 0xfff0:fff1 tpm1 channel 2 vtpm1ch2 0xfff2:fff3 tpm1 channel 1 vtpm1ch1 0xfff4:fff5 tpm1 channel 0 vtpm1ch0 0xfff6:fff7 icg vicg 0xfff8:fff9 low voltage detect vlvd 0xfffa:fffb irq virq 0xfffc:fffd swi vswi 0xfffe:ffff reset vreset
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 45 4.2 register addresses and bit assignments the registers in the mc9s08gbxxa/gtxxa are divided into these three groups: ? direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. ? high-page registers are used much less often, so they are located above 0x1800 in the memory map. this leaves more room in the direct page fo r more frequently used registers and variables. ? the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?0xffbf. nonvolatile register locations include: ? three values which are loaded in to working registers at reset ? an 8-byte backdoor comparison key which optionall y allows a user to gain controlled access to secure memory because the nonvolatile regi ster locations are flash memory, th ey must be erased and programmed like other flash memory locations. direct-page registers can be accessed with efficient direct addressing mode inst ructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page re gisters and control bits. the direct page registers in table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. because of th is, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-4 the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the ri ght. cells that are not associated with na med bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shad ed cells with dashes indi cate unused or reserved bit locations that could read as 1s or 0s.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 46 freescale semiconductor table 4-2. direct-page register summary (sheet 1 of 3) addressregister namebit 7654321bit 0 0x00 00 ptad ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 0x00 01 ptape ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 0x0002 ptase ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 0x00 03 ptadd ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 0x00 04 ptbd ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 0x00 05 ptbpe ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x00 06 ptbse ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 0x00 07 ptbdd ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 08 ptcd ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 0x00 09 ptcpe ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x00 0a ptcse ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 0x00 0b ptcdd ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x00 0c ptdd ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 0x00 0d ptdpe ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 0x00 0e ptdse ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 0x00 0f ptddd ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 0x00 10 pted pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 0x00 11 ptepe ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 0x00 12 ptese ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 0x00 13 ptedd ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 0x00 14 irqsc 0 0 irqedg irqpe irqf irqack irqie irqmod 0x00 15 reserved ? ? ? ? ? ? ? ? 0x00 16 kbi1sc kbedg7 kbedg6 kbedg5 kbedg4 kbf kback kbie kbimod 0x00 17 kbi1pe kbipe7 kbipe6 kbipe5 kbi pe4 kbipe3 kbipe2 kbipe1 kbipe0 0x00 18 sci1bdh 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 19 sci1bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 1a sci1c1 loops sciswai rsrc m wake ilt pe pt 0x00 1b sci1c2 tie tcie rie ilie te re rwu sbk 0x00 1c sci1s1 tdre tc rdrf idle or nf fe pf 0x00 1d sci1s2 0 0 0 0 0 0 0raf 0x00 1e sci1c3 r8 t8 txdir 0 orie neie feie peie 0x00 1f sci1d bit 7654321bit 0 0x00 20 sci2bdh 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 21 sci2bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 22 sci2c1 loops sciswai rsrc m wake ilt pe pt 0x00 23 sci2c2 tie tcie rie ilie te re rwu sbk 0x00 24 sci2s1 tdre tc rdrf idle or nf fe pf 0x00 25 sci2s2 0 0 0 0 0 0 0raf 0x00 26 sci2c3 r8 t8 txdir 0 orie neie feie peie 0x00 27 sci2d bit 7654321bit 0
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 47 0x00 28 spi1c1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 29 spi1c2 0 0 0 modfen bidiroe 0 spiswai spc0 0x00 2a spi1br 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 2b spi1s sprf 0 sptef modf 0 0 0 0 0x002c reserved 0 0 0 0 0 0 0 0 0x00 2d spi1d bit 7654321bit 0 0x002e reserved 0 0 0 0 0 0 0 0 0x002f reserved 0 0 0 0 0 0 0 0 0x00 30 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 31 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 32 tpm1cntl bit 7654321bit 0 0x00 33 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 34 tpm1modl bit 7654321bit 0 0x00 35 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 36 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 37 tpm1c0vl bit 7654321bit 0 0x00 38 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 39 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 3a tpm1c1vl bit 7654321bit 0 0x00 3b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 3c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 3d tpm1c2vl bit 7654321bit 0 0x003e ? 0x003f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 40 ptfd ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 0x00 41 ptfpe ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 0x0042 ptfse ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 0x00 43 ptfdd ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 0x00 44 ptgd ptgd7 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 0x00 45 ptgpe ptgpe7 ptgpe6 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 0x00 46 ptgse ptgse7 ptgse6 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 0x00 47 ptgdd ptgdd7 ptgdd6 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 0x00 48 icgc1 hgo range refs clks oscsten locd 0 0x00 49 icgc2 lolre mfd locre rfd 0x00 4a icgs1 clkst refst lols lock locs ercs icgif 0x00 4b icgs2 0 0 0 0 0 0 0 dcos 0x00 4c icgfltu 0 0 0 0f l t 0x00 4d icgfltl flt 0x00 4e icgtrm trim 0x004f reserved 0 0 0 0 0 0 0 0 table 4-2. direct-page register summary (sheet 2 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08gb60a data sheet, rev. 2 48 freescale semiconductor 0x00 50 atd1c atdpu djm res8 sgn prs 0x00 51 atd1sc ccf atdie atdco atdch 0x0052 atd1rh bit 7654321bit 0 0x00 53 atd1rl bit 7654321bit 0 0x00 54 atd1pe atdpe7 atdpe6 atdpe5 atdpe4 atdpe3 atdpe2 atdpe1 atdpe0 0x0055? 0x0057 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 58 iic1a addr 0 0x00 59 iic1f mult icr 0x00 5a iic1c iicen iicie mst tx txak rsta 0 0 0x00 5b iic1s tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iic1d data 0x005d ? 0x005f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl bit 7654321bit 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl bit 7654321bit 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl bit 7654321bit 0 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl bit 7654321bit 0 0x00 6b tpm2c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 6c tpm2c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 6d tpm2c2vl bit 7654321bit 0 0x00 6e tpm2c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 0x00 6f tpm2c3vh bit 15 14 13 12 11 10 9 bit 8 0x00 70 tpm2c3vl bit 7654321bit 0 0x00 71 tpm2c4sc ch4f ch4ie ms4b ms4a els4b els4a 0 0 0x00 72 tpm2c4vh bit 15 14 13 12 11 10 9 bit 8 0x00 73 tpm2c4vl bit 7654321bit 0 0x0074? 0x007f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 4-2. direct-page register summary (sheet 3 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 49 high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the dire ct addressable memory space, starting at 0x1800. nonvolatile flash regi sters, shown in table 4-4 , are located in the flash me mory. these registers include an 8-byte backdoor key which optionall y can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt wo rking registers in the high-page registers to control security and block protection options. table 4-3. high-page register summary addressregister namebit 7654321bit 0 0x1800 srs por pin cop ilop 0 icg lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0bdfr 0x1802 sopt cope copt stope ? 0 0 bkgdpe ? 0x1803 ? 0x1805 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1806 sdidh rev3 rev2 rev1 rev0 id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 srtisc rtif rtiack rticlks rtie 0 rtis2 rtis1 rtis0 0x1809 spmsc1 lvdf lvdack lvdie lvdre lvdse lvde 0 0 0x180a spmsc2 lvwf lvwack lvdv lvwv ppdf ppdack pdc ppdc 0x180b? 0x180f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7654321bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7654321bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7654321bit 0 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819? 0x181f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1820 fcdiv divld prdiv8 div5 div4 div3 div2 div1 div0 0x1821 fopt keyen fnored 0 0 0 0 sec01 sec00 0x1822 reserved ? ? ? ? ? ? ? ? 0x1823 fcnfg 0 0 keyacc 0 0 0 0 0 0x1824 fprot fpopen fpdis fps2 fps1 fps0 0 0 0 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 0x1827? 0x182b reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 4 memory mc9s08gb60a data sheet, rev. 2 50 freescale semiconductor provided the key enable (keyen) bit is 1, the 8-by te comparison key can be used to temporarily disengage memory security. this ke y mechanism can be accessed only th rough user code running in secure memory. (a security key cannot be entered directly through ba ckground debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if th e security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally throug h the background debug interface) and verifying that flash is blank. to a void returning to secure mode after the next reset, program the security bits (sec01:se c00) to the unsecured state (1:0). 4.3 ram the mc9s08gbxxa/gtxxa includes static ram. the locations in ram below 0x0100 can be accessed using the more efficient direct addr essing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or stop3 mode . at power-on or after wakeup from stop1, the cont ents of ram are uninitial ized. ram data is unaffect ed by any reset provided that the supply voltage does not drop be low the minimum value for ram retention. for compatibility with older m68hc05 mcus, the hcs08 resets the stack pointer to 0x00ff. in the mc9s08gbxxa/gtxxa, it is usually be st to re-initialize the stack point er to the top of the ram so the direct page ram can be used for frequently ac cessed ram variables and bit-addressable program variables. include the following 2- instruction sequence in your reset initia lization routine (where ramlast is equated to the highest address of the ram in the freescale- provided equate file). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource a nd is not accessible through bdm or through code executing from non-secure memory. see section 4.5, ?security ? for a detailed description of the security feature. 4.4 flash the flash memory is intended primar ily for program storage. in-circu it programming allows the operating program to be loaded into the flas h memory after final asse mbly of the application product. it is possible table 4-4. nonvolatile register summary addressregister namebit 7654321bit 0 0xffb0 ? 0xffb7 nvbackkey 8-byte comparison key 0xffb8 ? 0xffbc reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xffbd nvprot fpopen fpdis fps2 fps1 fps0 0 0 0 0xffbe reserved 1 1 this location is used to store the factory trim value for the icg. ? ? ? ? ? ? ? ? 0xffbf nvopt keyen fnored 0 0 0 0 sec01 sec00
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 51 to program the entire array through the single-wire background de bug interface. because no special voltages are needed for flash erase and programm ing operations, in-applicat ion programming is also possible through other software-cont rolled communication paths. for a more detailed discussion of in-circuit and in-applicati on programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor documen t order number hcs08rmv1/d. 4.4.1 features features of the flash memory include: ?flash size ? mc9s08gb60a/mc9s08gt60a ? 61268 byt es (120 pages of 512 bytes each) ? mc9s08gb32a/mc9s08gt32a? 32768 byt es (64 pages of 512 bytes each) ? single power supply program and erase ? command interface for fast program and erase operation ? up to 100,000 program/erase cycles at typical voltage and temperature ? flexible block protection ? security feature for flash and ram ? auto power-down for low-frequency read accesses 4.4.2 program and erase times before any program or erase comma nd can be accepted, the flash clock di vider register (fcdiv) must be written to set the internal clock for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see table 4.6.1 ). this register can be written only once, so normally this writ e is done during reset initialization. fcdiv cannot be written if the access e rror flag, faccerr in fstat, is set. the user must ensure that faccerr is not set be fore writing to the fcdiv register . one period of the resulting clock (1/f fclk ) is used by the command processor to time progr am and erase pulses. an integer number of these timing pulses is used by the command processo r to complete a program or erase command. table 4-5 shows program and erase times . the bus clock fre quency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk =1/f fclk . the times are shown as a number of cycles of fclk and as an ab solute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machine and enabling and disablin g of program and erase voltages. table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s 1 1 excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms
chapter 4 memory mc9s08gb60a data sheet, rev. 2 52 freescale semiconductor 4.4.3 program and erase command execution the steps for executing any of the co mmands are listed below. the fcdiv register must be initialized and any error flags cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash arra y. the address and data in formation from this write is latched into the flash interface. this write is a required first step in any command sequence. for erase and blank check commands, th e value of the data is not impor tant. for page erase commands, the address may be any address in the 512-byte page of flas h to be erased. for mass erase and blank check commands, the address can be any address in the flash memory. whole pages of 512 bytes are the smallest blocks of flas h that may be erased. in the 60k version, there are two instances where the size of a block that is a ccessible to the user is less than 512 bytes: the first page following ram, and the first page followi ng the high page registers. thes e pages are overl apped by the ram and high page registers, respectively. note do not program any byte in the flash mo re than once after a successful erase operation. reprogramming bits in a byt e which is already programmed is not allowed without first er asing the page in which th e byte resides or mass erasing the entire flash memory. pr ogramming without first erasing may disturb data stored in the flash. 2. write the command code for the desired command to fcmd. the five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr acc ess error flag which must be cleared before starting a new command. a strictly monitored procedure must be adhered to, or the command will not be accepted. this minimizes the possibility of any unintended change to the flash memory cont ents. the command complete flag (fccf) indicates when a command is complete. th e command sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a flowchart for executing all of the commands except for burst programming. the fcdiv register must be initia lized before using any flash commands. this must be done only once following a reset.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 53 figure 4-2. flash program and erase flowchart 4.4.4 burst program execution the burst program command is used to program sequential bytes of da ta in less time than would be required using the standard program command. this is possible because the high vol tage to the flash array does not need to be disabled betw een program operations. ordinarily, when a program or erase command is issued, an internal charge pum p associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the comma nd, the charge pump is turned off. when a burst program command is issued, the charge pump is enable d and then remains enabled after completion of the burst program operation if the fo llowing two conditions are met: 1. the next burst program command has been que ued before the current program operation has completed. 2. the next sequential address se lects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins wh en addresses a5 through a0 are all zero. the first byte of a series of sequential bytes being pr ogrammed in burst mode will take the same amount of time to program as a byte progr ammed in standard mode. subsequent bytes will program in the burst start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) only required once after reset.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 54 freescale semiconductor program time provided that the condi tions above are met. in the case the next sequential address is the beginning of a new row, the pr ogram time for that byte will be the st andard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command complete s, then the charge pump will be disabled and high voltage removed from the array. figure 4-3. flash burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) no yes new burst command ? 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 1 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) only required once after reset.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 55 4.4.5 access errors an access error occurs whenever the co mmand execution protocol is violated. any of the following specif ic actions will cause the access error fl ag (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. ? writing to a flash address before the internal fl ash clock frequency has been set by writing to the fcdiv register ? writing to a flash address while fcbef is not set (a new command cannot be started until the command buffer is empty.) ? writing a second time to a flash address before launching the previous command (there is only one write to flash for every command.) ? writing a second time to fcmd before launching the previous command (there is only one write to fcmd for every command.) ? writing to any flash control register other than fcmd afte r writing to a flash address ? writing any command code other than th e five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to fcmd ? accessing (read or write) any flas h control register other than th e write to fstat (to clear fcbef and launch the command) after writing the command to fcmd ? the mcu enters stop mode while a program or er ase command is in progress (the command is aborted.) ? writing the byte program, burst program, or pa ge erase command code (0x20, 0x25, or 0x40) with a background debug command while the mcu is secured (the background debug controller can only do blank check and mass erase commands when the mcu is secure.) ? writing 0 to fcbef to cancel a partial command 4.4.6 flash block protection block protection prevents program or erase changes for flash memory locations in a designated address range. mass erase is disabled when any block of flash is protecte d. the mc9s08gbxxa/gtxxa allows a block of memory at the end of flash, and/or the entire flash memory to be block protected. a disable control bit and a 3-bit control field, allows the user to set the size of this block. a separate control bit allows block protection of the entire flash memo ry array. all seven of these control bits are located in the fprot register (see section 4.6.4, ?flash protection register (fprot and nvprot) ? ). at reset, the high-page register ( fprot) is loaded with the contents of the nvprot location which is in the nonvolatile register block of the flash memory. the value in fprot cannot be changed directly from application software so a runaway program cannot alter the block protection settings. if the last 512 bytes of flash which includes the nvprot register is protected, the application program cannot alter the block protection settings (intentionally or unintentionally). the fprot control bits can be written by background debug commands to allow a way to erase a protected flash memory. one use for block protection is to block protect an area of flash memory for a bootloader program. this bootloader program then can be used to erase the rest of the flash memory and reprogram it. because the bootloader is protected, it remains intact even if mcu power is lost in the middle of an erase and reprogram operation.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 56 freescale semiconductor 4.4.7 vector redirection whenever any block protection is en abled, the reset and interrupt v ectors will be protected. vector redirection allows users to modify interrupt vector information wit hout unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to zero. fo r redirection to occur, at least so me portion but not all of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all of the interrupt vectors (memor y locations 0xffc0?0xfffd) are redirected, while the reset vector (0xfffe:ffff) is not. when more than 32k is protected, vector redirecti on must not be enabled. for example, if 512 bytes of flash are protected, the protected address region is from 0xfe00 through 0xffff. the interrupt vectors (0x ffc0?0xfffd) are redirected to th e locations 0xfdc0?0xfdfd. now, if an spi interrupt is taken for in stance, the values in the locations 0xfde0:fde1 are used for the vector instead of the values in the locations 0xffe0:ffe1. this allows the user to reprogram the unprotected portion of the flash with new program code includi ng new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5 security the mc9s08gbxxa/gtxxa includes circ uitry to prevent unauthor ized access to the c ontents of flash and ram memory. when security is engaged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are consider ed unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory lo cation with a program executing from an unsecured memory space or through the background debug interface are bloc ked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the stat e of two nonvolatile register bits (sec01:sec00) in the fopt register. during reset, the contents of th e nonvolatile location nvopt are copied from flash into the working fopt register in hi gh-page register space. a user engages security by programming the nvopt location which can be done at the same time the flash memory is programmed. the 1:0 state disengages security while th e other three combinations engage security. notice the erased state (1:1) makes the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec00 bit to 0 in nvopt so sec01: sec00 = 1:0. this would al low the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can still be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd/ms low at the rising edge of reset. a user can choose to allow or disallow a securi ty unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile ke yen bit in nvopt/fopt is 0, the b ackdoor key is disabled and there is no way to disengage security without completely erasing all flash locations . if keyen is 1, a secure user program can temporar ily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbac kkey+7) as values to be compared against the key rather than as the fi rst step in a flash pr ogram or erase command.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 57 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be done in order, starting with the value for nvbackkey and ending with nvbackkey+7. sthx should not be used for thes e writes because these writes cannot be done on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication in terface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was just written matches the key stored in the flash locations , sec01:sec00 are automatically ch anged to 1:0 and security will be disengaged until the next reset. the security key can be written only from ram, so it cannot be entered through background commands without the cooperation of a secure user program. the flash memory cannot be accessed by read operations while keyacc is set. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register sp ace so users can program these locat ions just as th ey would program any other flash memory lo cation. the nonvolatile register s are in the same 512-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects th e backdoor comparison key. block protects cannot be changed from user application programs, so if th e vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through the background debug interface by performing these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash, if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0. 4.6 flash registers and control bits the flash module has nine 8-bit regi sters in the high-page register space, three locations in the nonvolatile register space in flash memory that are copied into three corresponding hi gh-page control registers at reset. there is also an 8-byte comparis on key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all flash registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file nor mally is used to translate these names into the appropriate absolute addresses. 4.6.1 flash clock divider register (fcdiv) bit 7 of this register is a read-onl y status flag. bits 6 through 0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 58 freescale semiconductor if prdiv8 = 0 ? f fclk = f bus ([div5:div0] + 1) eqn. 4-1 if prdiv8 = 1 ? f fclk = f bus (8 ([div5:div0] + 1)) eqn. 4-2 76543210 rdivld prdiv8 div5 div4 div3 div2 div1 div0 w r e s e t00000000 = unimplemented or reserved figure 4-4. flash clock divider register (fcdiv) table 4-6. fcdiv field descriptions field description 7 divld divisor loaded status flag ? when set, this read-only status flag indicates that the fcdiv register has been written since reset. reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash. 1 fcdiv has been written since reset; erase and program operations enabled for flash. 6 prdiv8 prescale (divide) flash clock by 8 0 clock input to the flash clock divider is the bus rate clock. 1 clock input to the flash clock divider is the bus rate clock divided by 8. 5 div[5:0] divisor for flash clock divider ? the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div5:div0 field plus one. the resulting frequency of the internal flash clock must fall within the range of 200 kh z to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this internal flas h clock, which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 and equation 4-2 . ta b l e 4 - 7 shows the appropriate values for prdiv8 and div5:div0 for selected bus frequencies. table 4-7. flash clock divider settings f bus prdiv8 (binary) div5:div0 (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 59 4.6.2 flash options register (fopt and nvopt) during reset, the contents of th e nonvolatile location nvopt are copi ed from flash into fopt. bits 5 through 2 are not used and always read 0. this register may be read at a ny time, but writes have no meaning or effect. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. 76543210 r keyen fnored 0000 sec01 sec00 w reset this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-5. flash options register (fopt) table 4-8. fopt field descriptions field description 7 keyen backdoor key mechanism enable ? when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) firmware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.5, ?security .? 0 no backdoor key access allowed. 1 if user firmware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7, in that order), security is te mporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ? when this bit is 1, vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 1:0 sec0[1:0] security state code ? this 2-bit field determines the security state of the mcu as shown below. when the mcu is secure, the contents of ram and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. for more detailed information about security, refer to section 4.5, ?security .? 00 secure 01 secure 10 unsecured 11 secure sec0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of flash.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 60 freescale semiconductor 4.6.3 flash configurat ion register (fcnfg) bits 7 through 5 may be read or wri tten at any time. bits 4 through 0 always read 0 and cannot be written. 4.6.4 flash protection register (fprot and nvprot) during reset, the contents of the nonvolatile location nvprot is copi ed from flash into fprot. bits 0, 1, and 2 are not used and each always reads as 0. this register may be r ead at any time, but user program writes have no meaning or effect. bac kground debug commands can write to fprot. 76543210 r0 0 keyacc 00000 w r e s e t00000000 = unimplemented or reserved figure 4-6. flash configur ation register (fcnfg) table 4-9. fcnfg field descriptions field description 5 keyacc enable writing of access key ? this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.5, ?security .? 0 writes to 0xffb0?0xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?0xffb7) are interpreted as comparison key writes. reads of the flash return invalid data. 76543210 r fpopen fpdis fps2 fps1 fps0 0 0 0 w (1) 1 background commands can be used to change the contents of these bits in fprot. ( 1 )( 1 )( 1 )( 1 ) reset this register is loaded from nonvolatile location nvprot during reset. = unimplemented or reserved figure 4-7. flash protection register (fprot) table 4-10. fprot field descriptions field description 7 fpopen open unprotected flash for program/erase 0 entire flash memory is block protec ted (no program or erase allowed). 1 any flash location, not otherwise block protec ted or secured, may be erased or programmed.
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 61 6 fpdis flash protection disable 0 flash block specified by fps2:fps0 is block protected (program and erase not allowed). 1 no flash block is protected. 5:3 fps[2:0] flash protect size selects ? when fpdis = 0, this 3-bit field determines the size of a protected block of flash locations at the high address end of the flash (see ta bl e 4 - 1 1 ). protected flash locations cannot be erased or programmed. table 4-11. high address protected block fps2:fps1:fps0 protected address range protected block size redirected vectors 1,2 1 no redirection if fpopen = 0, or fnored = 1. 2 reset vector is not redirected. 0:0:0 0xfe00?0xffff 512 bytes 0xfdc0?0xfdfd 0:0:1 0xfc00?0xffff 1024 bytes 0xfbc0?0xfbfd 0:1:0 0xf800?0xffff 2048 bytes 0xf7c0?0xf7fd 0:1:1 0xf000?0xffff 4096 bytes 0xefc0?0xeffd 1:0:0 0xe000?0xffff 8192 bytes 0xdfc0?0xdffd 1:0:1 0xc000?0xffff 16384 bytes 0xbfc0?0xbffd 3 3 32k and 60k devices only. 1:1:0 0x8000?0xffff 32768 bytes 0x7fc0?0x7ffd 4 4 60k devices only. 1:1:1 0x182c?0xffff 59,348 bytes no redirection allowed table 4-10. fprot field descriptions (continued) field description
chapter 4 memory mc9s08gb60a data sheet, rev. 2 62 freescale semiconductor 4.6.5 flash status register (fstat) bits 3, 1, and 0 always read 0 and writes have no meani ng or effect. the remaining fi ve bits are status bits that can be read at any time. writes to these bits have special meanings that are discussed in the bit descriptions. 76543210 r fcbef fccf fpviol faccerr 0fblank0 0 w r e s e t11000000 = unimplemented or reserved figure 4-8. flash status register (fstat) table 4-12. fstat field descriptions field description 7 fcbef flash command buffer empty flag ? the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command may be written to the command buffer. 6 fccf flash command complete flag ? fccf is set automatically when t he command buffer is empty and no command is being processed. fccf is cleared automatically when a new co mmand is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag ? fpviol is set automatically when fcbef is cleared to register a command that attempts to erase or program a location in a protecte d block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location. 4 faccerr access error flag ? faccerr is set automatically when the proper command sequence is not followed exactly (the erroneous command is ignor ed), if a program or erase operat ion is attempted before the fcdiv register has been initialized, or if the mcu enters stop while a command was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.4.5, ?access errors .? faccerr is cleared by writing a 1 to faccerr. writ ing a 0 to faccerr has no meaning or effect. 0 no access error has occurred. 1 an access error has occurred. 2 fblank flash verified as all blank (erased) flag ? fblank is set automatically at the conclusion of a blank check command if the entire flash array was verified to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fb lank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all 0xff).
chapter 4 memory mc9s08gb60a data sheet, rev. 2 freescale semiconductor 63 4.6.6 flash command register (fcmd) only five command codes are recognized in normal us er modes as shown in table 4-14 . refer to section 4.4.3, ?program and erase command execution ? for a detailed discus sion of flash programming and erase operations. all other command codes are illega l and generate an access error. it is not necessary to perform a blank check comma nd after a mass erase operation. only blank check is required as part of the se curity unlocking mechanism. 76543210 r00000000 w fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 reset00000000 figure 4-9. flash command register (fcmd) table 4-13. fcmd field descriptions field description 7:0 fcmd[7:0] see ta bl e 4 - 1 4 for a description of fcmd[7:0]. table 4-14. flash commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog byte program ? burst mode 0x25 mburstprog page erase (512 bytes/page) 0x40 mpageerase mass erase (all flash) 0x41 mmasserase
chapter 4 memory mc9s08gb60a data sheet, rev. 2 64 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 65 chapter 5 resets, interrupts, and system configuration 5.1 introduction this section discusses basic reset a nd interrupt mechanisms and the various sources of reset and interrupts in the mc9s08gbxxa/gtxxa. some in terrupt sources from peripheral m odules are discussed in greater detail within other sections of this data manual. this section gathers basic information about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog and real-time interrupt (rti), are not part of on-chip peripheral systems with their own se ctions but are part of the system control logic. 5.2 features reset and interrupt features include: ? multiple sources of reset for flexible sy stem configuration an d reliable operation: ? power-on detection (por) ? low voltage detection (lvd) with enable ? external reset pin with enable ? cop watchdog with enable and two timeout choices ? illegal opcode ? serial command from a background debug host ? reset status register (srs) to indicate source of most recent reset ? separate interrupt vectors for each module (reduces polling overhead) (see table 5-1 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers ar e forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral m odules are disabled and i/o pins are initially configured as general-purpose high-impedance input s with pullup devices disa bled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system c ontrol settings. sp is forced to 0x00ff at reset. the mc9s08gbxxa/gtxxa has seven sources for reset: ? power-on reset (por) ? low-voltage detect (lvd) ? computer operating properly (cop) timer
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 66 freescale semiconductor ? illegal opcode detect ? background debug forced reset ? the reset pin (reset ) ? clock generator loss of lock and loss of clock reset each of these sources, with the ex ception of the background debug forced reset, has an associated bit in the system reset status register. wh enever the mcu enters reset, the internal clock gene rator (icg) module switches to self-clocked m ode with the frequency of f self_reset selected. the reset pin is driven low for 34 internal bus cycles where the inte rnal bus frequency is half the icg frequency. after the 34 cycles are completed, the pin is released and will be pulled up by the internal pull up resistor, unless it is held low externally. after the pin is released, it is sampled afte r another 38 cycles to dete rmine whether the reset pin is the cause of the mcu reset. 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset wh en the application software fails to execute as expected. to prevent a system reset from the cop time r (when it is enabled), ap plication software must reset the cop timer periodically. if the application program gets lost and fails to reset the cop before it times out, a system reset is generated to force the system back to a known starting point. the cop watchdog is enabled by the co pe bit in sopt (see section 5.8.4, ?system optio ns register (sopt) ? for additional information). the cop timer is reset by writi ng any value to the address of srs. this write does not affect the data in the read-only srs. instead, the act of writing to this address is decoded and sends a reset signal to the cop timer. after any reset, the cop timer is enab led. this provides a reliable way to detect code that is not executing as intended. if the cop watchdog is not used in an a pplication, it can be disabled by clearing the cope bit in the write-once sopt register. also, the copt b it can be used to choose one of two timeout periods (2 18 or 2 13 cycles of the bus rate clock). even if the applic ation will use the reset de fault settings in cope and copt, the user should st ill write to write-onc e sopt during reset initializa tion to lock in the settings. that way, they cannot be changed accidental ly if the application program gets lost. the write to srs that services (cl ears) the cop timer should not be plac ed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. when the mcu is in active background mode , the cop timer is temporarily disabled. 5.5 interrupts interrupts provide a way to save the current cpu status and registers, ex ecute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caus ed by hardware events such as an edge on the irq pin or a timer-overflow event. the debug module can also generate an swi under certain ci rcumstances. if an event occurs in an enabled interrupt source, an associated read-only status flag will become set. the cpu will not respond until and unless the local in terrupt enable is set to 1 to enable the interrupt. the i bit
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 67 in the ccr is 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which masks (prevents) all maskable interrupt sources. the user program initialize s the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a qua lified interrupt request, it completes the current in struction before responding to the interrupt. the inte rrupt sequence follows the same cycle-by- cycle sequence as the swi instruction and consists of: ? saving the cpu registers on the stack ? setting the i bit in the ccr to mask further interrupts ? fetching the interrupt vector for the highest-priority interrupt that is currently pending ? filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restor ed from the value stacked on entry to the isr. in rare cases, the i bit may be cleared inside an isr (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the fi rst service routine to finish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. the interrupt service routine ends wi th a return-from-interrupt (rti) in struction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information off the stack. note for compatibility with the m68hc08, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service rou tine (isr) and restore it just before the rti that is used to return from the isr. when two or more interrupts are pending when the i bit is cleared, the highest prio rity source is serviced first (see table 5-1 ). 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next av ailable byte location on the stack. the curr ent values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next avai lable location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 68 freescale semiconductor figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu fills the instruction pipeline by reading th ree bytes of program information, starting from the pc address ju st recovered from the stack. the status flag causing the interrupt must be acknow ledged (cleared) before returning from the isr. typically, the flag should be cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after comp letion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irqsc status and control register. when the irq function is enabled, synchronous logic m onitors the pin for edge- only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 pin configuration options the irq pin enable (irqpe) control bit in the irqsc register must be 1 for the irq pin to act as the interrupt request (irq) input. when th e pin is configured as an irq i nput, the user can choose the polarity of edges or levels detected (irqe dg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or only se ts the irqf flag (which can be polled by software). when the irq pin is configured to detect rising edges, an optional pulldown resi stor is available rather than a pullup resistor. bih and bil instructions may be used to detect the level on the irq pin when the pin is configured to act as the irq input. note the voltage measured on the pulled up irq pin may be as low as v dd ? 0.7 v. the internal gates connected to this pin are pulled all the way to v dd . all other pins with enabled pullup resist ors will have an unl oaded measurement of v dd . condition code register accumulator index register (low byte x) program counter high * high byte (h) of index regist er is not automatically stacked. * program counter low 2 2 2 2 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 69 5.5.2.2 edge and level sensitivity the irqmod control bit re-configures th e detection logic so it detects edge events and pin levels. in this edge detection mode, the irqf status flag becomes set when an edge is detected (when the irq pin changes from the deasse rted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the irq pin rema ins at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-1 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byt e of the address for the interrupt service routine is located at the first address in the vector address column, and the lo w-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated flag bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will finish the current instruction, stack th e pcl, pch, x, a, and ccr cpu registers, set the i bit, and then fetch the interru pt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 70 freescale semiconductor table 5-1. vector summary vector priority vector number address (high/low) vector name module source enable description lower higher 26 through 31 0xffc0/ffc1 through 0xffca/ffcb unused vector space (available for user program) 25 0xffcc/ffcd vrti system control rtif rtie real-time interrupt 24 0xffce/ffcf viic1 iic iicis iicie iic control 23 0xffd0/ffd1 vatd1 atd coco aien ad conversion complete 22 0xffd2/ffd3 vkeyboard1 kbi kbf kbie keyboard pins 21 0xffd4/ffd5 vsci2tx sci2 tdre tc tie tcie sci2 transmit 20 0xffd6/ffd7 vsci2rx sci2 idle rdrf ilie rie sci2 receive 19 0xffd8/ffd9 vsci2err sci2 or nf fe pf orie nfie feie pfie sci2 error 18 0xffda/ffdb vsci1tx sci1 tdre tc tie tcie sci1 transmit 17 0xffdc/ffdd vsci1rx sci1 idle rdrf ilie rie sci1 receive 16 0xffde/ffdf vsci1err sci1 or nf fe pf orie nfie feie pfie sci1 error 15 0xffe0/ffe1 vspi1 spi spif modf sptef spie spie sptie spi 14 0xffe2/ffe3 vtpm2ovf tpm2 tof toie tpm2 overflow 13 0xffe4/ffe5 vtpm2ch4 tpm2 ch4f ch4ie tpm2 channel 4 12 0xffe6/ffe7 vtpm2ch3 tpm2 ch3f ch3ie tpm2 channel 3 11 0xffe8/ffe9 vtpm2ch2 tpm2 ch2f ch2ie tpm2 channel 2 10 0xffea/ffeb vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 9 0xffec/ffed vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 8 0xffee/ffef vtpm1ovf tp m1 tof toie tpm1 overflow 7 0xfff0/fff1 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 6 0xfff2/fff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4/fff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6/fff7 vicg icg icgif (lols/locs) lolre/locre icg 3 0xfff8/fff9 vlvd system control lvdf lvdie low-voltage detect 2 0xfffa/fffb virq irq irqf irqie irq pin 1 0xfffc/fffd vswi core swi instruction ? software interrupt 0 0xfffe/ffff vreset system control cop lv d reset pin illegal opcode cope lv d r e ? ? watchdog timer low-voltage detect external pin illegal opcode
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 71 5.6 low-voltage detect (lvd) system the mc9s08gbxxa/gtxxa includes a system to prot ect against low voltage conditions to protect memory contents and control mcu sy stem states during supply voltage variations. the system comprises a power-on reset (por) circ uit and an lvd circuit w ith a user selectable tr ip voltage, either high (v lvdh ) or low (v lvdl ). the lvd circuit is enabled when lvde in spm sc1 is high and the trip voltage is selected by lvdv in spmsc2. the lvd is di sabled upon entering any of the stop modes unl ess the lvdse bit is set. if lvdse and lvde are both set, then th e mcu cannot enter stop1 or stop2, and the current consumption in stop3 with the lvd enabled will be greater. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the v por level, the por circuit will cause a rese t condition. as the supply voltage rises, the lvd circuit will hold the chip in reset until the supply has risen above the v lvdl level. both the por bit and the lvd bit in srs are set following a por. 5.6.2 lvd reset operation the lvd can be configured to generate a reset upon detection of a low vol tage condition by setting lvdre to 1. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the level determined by lvdv. the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 lvd interrupt operation when a low voltage condition is dete cted and the lvd circuit is configured for interrupt operation (lvde set, lvdie set, and lvdre clear), then lvdf will be set and an lvd interrupt will occur. 5.6.4 low-voltage warning (lvw) the lvd system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above, the lvd voltage. the lvw does not have an interrupt associated with it. there are two user sel ectable trip voltages for the lvw, one high (v lvwh ) and one low (v lvwl ). the trip voltage is selected by lvwv in spmsc2. 5.7 real-time interrupt (rti) the real-time interrupt function can be used to generate periodic interrupts based on a multiple of the source clock's period. the rti has two source clock choices, the external clock input (icgerclk) to the icg or the rti's own internal cloc k. the rti can be used in run, wait , stop2 and stop3 modes. it is not available in stop1 mode. in run and wait modes, only the external clock can be used as the rti's clock source. in stop2 mode, only the internal rti clock can be used. in stop3, either the external clock or internal rti clock can be used. when using the external oscillator in stop3 mode, it must be enabled in stop (oscsten = 1) and
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 72 freescale semiconductor configured for low bandwidth oper ation (range = 0). if active bd m mode is enabled in stop3, the internal rti clock is not available. the srtisc register includes a r ead-only status flag, a write-only ac knowledge bit, and a 3-bit control value (rtis2:rtis1:rtis0) used to select one of seven rti periods. th e rti has a local interrupt enable, rtie, to allow masking of the real-time interrupt. the module can be disabled by writing 0:0:0 to rtis2:rtis1:rtis0 in which case the clock source input is disabled a nd no interrupts will be generated. see section 5.8.6, ?system real-time interrupt status and control register (srtisc) ,? for detailed information about this register. 5.8 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space a nd eight 8-bit registers in th e high-page register space are related to reset and interrupt systems. refer to the direct-page register summary in chapter 4, ?memory ? of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. some control bits in the sopt and spmsc2 registers are related to m odes of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?modes of operation .?
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 73 5.8.1 interrupt pin request status and control register (irqsc) this direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-on ly bit. these bits are used to configure the ir q function, report status, and acknowledge irq events. 76543210 r0 0 irqedg irqpe irqf 0 irqie irqmod w irqack r e s e t00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc) table 5-2. irqsc field descriptions field description 5 irqedg interrupt request (irq) edge select ? this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the ir q pin is enabled as the irq input and is configured to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable ? this read/write control bit enables the irq pin function. when this bit is set, the irq pin can be used as an interrupt request. also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the irqmod bit. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ? this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 2 irqack irq acknowledge ? this write-only bit is used to acknowledge in terrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detecti on is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ? this read/write control bit determines whether irq events generate a hardware interrupt request. 0 hardware interrupt requests from irqf disabled (use polling). 1 hardware interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ? this read/write control bit selects eith er edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see section 5.5.2.2, ?edge and level sensitivity ? for more details. 0 irq event on falling edges or rising edges only. 1 irq event on falling edges and low levels or on rising edges and high levels.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 74 freescale semiconductor 5.8.2 system reset status register (srs) this register includes six read-only status flags to i ndicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdf r register, none of the status bits in srs will be set. writing any value to this register address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset. figure 5-3. system reset status (srs) 76543210 r por pin cop ilop 0 icg lvd 0 w writing any value to simrs address clears cop watchdog timer. power-on reset: 10000010 low-voltage reset: u0000010 any other reset: 0note (1) 1 any of these reset sources that are active at the time of reset will cause the corresp onding bit(s) to be set; bits correspondi ng to sources that are not active at the time of reset will be cleared. note (1) note (1) 0note (1) 00 u = unaffected by reset table 5-3. srs field descriptions field description 7 por power-on reset ? reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ? reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog ? reset was caused by the cop watchdog timer timing out. this reset source may be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode ? reset was caused by an attempt to execut e an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt regi ster. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 75 5.8.3 system background debug force reset register (sbdfr) this register contains a single write-only c ontrol bit. a serial background command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. figure 5-4. system background debug force reset register (sbdfr) 2 icg internal clock gene ration module reset ? reset was caused by an icg module reset. 0 reset not caused by icg module. 1 reset caused by icg module. 1 lv d low voltage detect ? if the lvd reset is enabled (lvde = lvdre = 1) and the supply drops below the lvd trip voltage, an lvd reset occurs. the lvd function is disabl ed when the mcu enters stop. to maintain lvd operation in stop, the lvdse bit must be set. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background debug commands, not from user programs. r e s e t00000000 = unimplemented or reserved table 5-4. sbdfr field descriptions field description 0 bdfr background debug force reset ? a serial background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit fo rces an mcu reset. this bit cannot be written from a user program. table 5-3. srs field descriptions (continued) field description
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 76 freescale semiconductor 5.8.4 system options register (sopt) this register may be read at any time. bits 3 a nd 2 are unimplemented and always read 0. this is a write-once register so only the first write after reset is honored. any subs equent attempt to write to sopt (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt should be written during the us er?s reset initialization program to set th e desired controls even if the desired settings are the same as the reset settings. 76543210 r cope copt stope 00 bkgdpe w r e s e t11010011 = unimplemented or reserved figure 5-5. system options register (sopt) table 5-5. sopt field descriptions field description 7 cope cop watchdog enable ? this write-once bit defaults to 1 after reset. 0 cop watchdog timer disabled. 1 cop watchdog timer enabled (force reset on timeout). 6 copt cop watchdog timeout ? this write-once bit defaults to 1 after reset. 0 short timeout period selected (2 13 cycles of busclk). 1 long timeout period selected (2 18 cycles of busclk). 5 stope stop mode enable ? this write-once bit defaults to 0 after rese t, which disables stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled. 1 bkgdpe background debug mode pin enable ? the bkgdpe bit enables the ptg0/bkgd/ms pin to function as bkgd/ms. when the bit is clear, the pin will function as ptg0 , which is an output-only general-purpose i/o. this pin always defaults to bkgd/ms function after any reset. 0 bkgd pin disabled. 1 bkgd pin enabled.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 77 5.8.5 system device identificati on register (sdidh, sdidl) this read-only register is included so host developm ent systems can identify the hcs08 derivative and revision number. this allows the development soft ware to recognize where specific memory blocks, registers, and control bits are located in a target mcu. figure 5-6. system device identification register high (sdidh) 76543210 r rev3 rev2 rev1 rev0 id11 id10 id9 id8 w reset 0 1 1 the revision number that is hard coded into these bits reflects the current silicon revision level. 0 (1) 0 (1) 0 (1) 0000 = unimplemented or reserved table 5-6. sdidh field descriptions field description 7:4 rev[3:0] revision number ? the high-order 4 bits of address 0x1806 are hard coded to reflect the current mask set revision number (0?f). 3:0 id[11:8] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08gbxxa/gtxxa is hard coded to t he value 0x002. see also id bits in ta bl e 5 - 7 . 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w r e s e t00000010 = unimplemented or reserved figure 5-7. system device identification register low (sdidl) table 5-7. sdidl field descriptions field description 3:0 id[7:0] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08gbxxa/gtxxa is hard coded to t he value 0x002. see also id bits in ta bl e 5 - 6 .
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 78 freescale semiconductor 5.8.6 system real-time interrupt stat us and control register (srtisc) this register contains one read- only status flag, one wr ite-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. 76543210 r rtif 0 rticlks rtie 0 rtis2 rtis 1 rtis 0 w rtiack r e s e t00000000 = unimplemented or reserved figure 5-8. system rti status and control register (srtisc) table 5-8. srtisc field descriptions field description 7 rtif real-time interrupt flag ? this read-only status bit indicates the periodic wakeup timer has timed out. 0 periodic wakeup timer not timed out. 1 periodic wakeup timer timed out. 6 rtiack real-time interrupt acknowledge ? this write-only bit is used to ac knowledge real-time interrupt request (write 1 to clear rtif). writing 0 has no meaning or effect. reads always return 0. 5 rticlks real-time interrupt clock select ? this read/write bit selects the cloc k source for the real-time interrupt. 0 real-time interrupt request clock source is internal oscillator. 1 real-time interrupt request clock source is external clock. 4 rtie real-time interrupt enable ? this read-write bit enables real-time interrupts. 0 real-time interrupts disabled. 1 real-time interrupts enabled. 2:0 rtis[2:0] real-time interrupt period selects ? these read/write bits select the wakeup period for the rti. one clock source for the real-time interrupt is its own internal cloc k source, which oscillates with a period of approximately t rti and is independent of other mcu clock sources. using an external clock source the delays will be crystal frequency divided by value in rtis2:rtis1:rtis0. see ta bl e 5 - 9 . table 5-9. real-time interrupt period rtis2:rtis1:rtis0 internal clock source 1 (t rti = 1 ms, nominal) 1 see ta b l e a - 1 0 t rti in appendix a, ?electrical characteristics ,? for the tolerance on these values. external clock source 2 period = t ext 2 t ext is based on the external clock source, resonator, or crystal selected by the icg configuration. see ta b l e a - 9 for details. 0:0:0 disable periodic wakeup timer disable periodic wakeup timer 0:0:1 8 ms t ext x 256 0:1:0 32 ms t ex x 1024 0:1:1 64 ms t ex x 2048 1:0:0 128 ms t ex x 4096 1:0:1 256 ms t ext x 8192 1:1:0 512 ms t ext x 16384 1:1:1 1.024 s t ex x 32768
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 freescale semiconductor 79 5.8.7 system power management status and control 1 register (spmsc1) figure 5-9. system power management status and control 1 register (spmsc1) 76543210 rlvdf 0 lvdie lvdre 1 1 this bit can be written only one time after reset. additional writes are ignored. lv d s e (1) lv d e (1) 00 w lv dac k r e s e t00011100 = unimplemented or reserved table 5-10. spmsc1 field descriptions field description 7 lv d f low-voltage detect flag ? provided lvde = 1, this read-only status bit indicates a low-voltage detect event. 6 lv dac k low-voltage detect acknowledge ? this write-only bit is used to acknowledge low voltage detection errors (write 1 to clear lvdf). reads always return 0. 5 lv d i e low-voltage detect interrupt enable ? this read/write bit enables hardware interrupt requests for lvdf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvdf = 1. 4 lvdre low-voltage detect reset enable ? this read/write bit enables lvdf events to generate a hardware reset (provided lvde = 1). 0 lvdf does not generate hardware resets. 1 force an mcu reset when lvdf = 1. 3 lv d s e low-voltage detect stop enable ? provided lvde = 1, this read/writ e bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lv d e low-voltage detect enable ? this read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled.
chapter 5 resets, interrupts, and system configuration mc9s08gb60a data sheet, rev. 2 80 freescale semiconductor 5.8.8 system power management status and control 2 register (spmsc2) this register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the mcu. figure 5-10. system power management status and control 2 register (spmsc2) 76543210 r lv w f 0 lv dv lv w v ppdf 0 pdc ppdc w lv wac k ppdack power-on reset: 0 (1) 1 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w . 0000000 lvd reset: 0 (1) 0uu0000 any other reset: 0 (1) 0uu0000 = unimplemented or reserved u = unaffected by reset table 5-11. spmsc2 field descriptions field description 7 lv w f low-voltage warning flag ? the lvwf bit indicates the low voltage warning status. 0 low voltage warning not present. 1 low voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ? the lvwack bit is the low-voltage warning acknowledge. writing a 1 to lvwack clears lvwf to 0 if a low voltage warning is not present. 5 lv dv low-voltage detect voltage select ? the lvdv bit selects the lvd trip point voltage (v lv d ). 0 low trip point selected (v lv d = v lvd l ). 1 high trip point selected (v lvd = v lv d h ). 4 lv w v low-voltage warning voltage select ? the lvwv bit selects the lvw trip point voltage (v lv w ). 0 low trip point selected (v lv w = v lv w l ). 1 high trip point selected (v lvw = v lv w h ). 3 ppdf partial power down flag ? the ppdf bit indicates that the mcu has exited the stop2 mode. 0 not stop2 mode recovery. 1 stop2 mode recovery. 2 ppdack partial power down acknowledge ? writing a 1 to ppdack clears the ppdf bit. 1 pdc power down control ? the write-once pdc bit controls entry in to the power down (stop2 and stop1) modes. 0 power down modes are disabled. 1 power down modes are enabled. 0 ppdc partial power down control ? the write-once ppdc bit controls which power down mode, stop1 or stop2, is selected. 0 stop1, full power down, mode enabled if pdc set. 1 stop2, partial power down, mode enabled if pdc set.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 81 chapter 6 parallel input/output 6.1 introduction this section explains software c ontrols related to parallel input/output (i/o). the mc9s08gbxxa has seven i/o ports which include a total of 56 general-purpose i/o pins (one of these pins is output only). the mc9s08gtxxa has six i/o ports which include a tota l of up to 39 general-pur pose i/o pins (one pin, ptg0, is output only). see chapter 2, ?pins and connections ,? for more information about the logic and hardware aspects of these pins. many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts. when these other modules are not controlling the port pins, they revert to general-purpose i/o control. for each i/o pin, a port data bit provides access to input (read) and output (write) data, a data directi on bit controls the direction of the pin, and a pullup enab le bit enables an internal pullup device (provided the pin is configured as an input ), and a slew rate control bit controls the rise and fall times of the pins. note not all general-purpose i/o pins are av ailable on all packages. to avoid extra current drain from floating input pins, the user?s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unc onnected pins to outputs so the pins do not float.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 82 freescale semiconductor figure 6-1. block diagram highlighting parallel input/output pins ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq note: not all pins are bonded out in all packages. see table 2-2 for complete details. = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 83 6.2 features parallel i/o features, depending on package choice, include: ? a total of 56 general-purpose i/o pins in seven ports (ptg0 is output only) ? high-current drivers on port c and port f pins ? hysteresis input buffers ? software-controlled pullups on each input pin ? software-controlled sl ew rate output buffers ? eight port a pins shared with kbi1 ? eight port b pins shared with atd1 ? eight high-current port c pins shared with sci2 and iic1 ? eight port d pins shared with tpm1 and tpm2 ? eight port e pins shared with sci1 and spi1 ? eight high-current port f pins ? eight port g pins shared wi th extal, xtal, and bkgd/ms 6.3 pin descriptions the mc9s08gbxxa/gtxxa has a total of 56 parallel i/o pins (one is output only) in seven 8-bit ports (pta?ptg). not all pins are bonded out in al l packages. consult the pin assignment in chapter 2, ?pins and connections,? for available parallel i/o pins. all of th ese pins are available for general-purpose i/o when they are not used by other on-chip peripheral systems. after reset, bkgd/ms is enabled and therefore is not usable as an out put pin until bkgdpe in sopt is cleared. the rest of the peripheral functions are disabled. after reset, al l data direction and pullup enable controls are set to 0s. these pins default to being high-impedance inputs with on-chip pullup devices disabled. the following paragraphs discuss each port and the software controls that determine each pin?s use. 6.3.1 port a and keyboard interrupts figure 6-2. port a pin names port a is an 8-bit port shared among the kbi keyboard interrupt inputs and gene ral-purpose i/o. any pins enabled as kbi inputs will be forced to act as inputs. port a pins are available as general-purpose i/o pins controlled by the port a data (ptad), data direction (ptadd), pullup enable (ptape ), and slew rate control (p tase) registers. refer to section 6.4, ?parallel i/o controls ,? for more information about general-purpose i/o control. port a bit 7654321bit 0 mcu pin: pta7/ kbi1p7 pta6/ kbi1p6 pta5/ kbi1p5 pta4/ kbi1p4 pta3/ kbi1p3 pta2/ kbi1p2 pta1/ kbi1p1 pta0/ kbi1p0
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 84 freescale semiconductor port a can be configured to be ke yboard interrupt input pins. refer to chapter 9, ?keyboard interrupt (s08kbiv1) ,? for more information about using por t a pins as keyboard interrupts pins. 6.3.2 port b and analog to digital converter inputs j figure 6-3. port b pin names port b is an 8-bit port shared am ong the atd inputs and general-purpose i/o. any pin enabled as an atd input will be forced to act as an input. port b pins are available as genera l-purpose i/o pins contro lled by the port b data (ptbd), data direction (ptbdd), pullup enable (ptbpe), and slew rate control (ptbse) registers. refer to section 6.4, ?parallel i/o controls ,? for more information about general-purpose i/o control. when the atd module is enabled, anal og pin enables are used to specify which pins on port b will be used as atd inputs. refer to chapter 14, ?analog-to-dig ital converter (s08atdv3) ,? for more information about using port b pins as atd pins. 6.3.3 port c and sci2, iic, and high-current drivers figure 6-4. port c pin names port c is an 8-bit port which is shared among the sci2 and iic1 modules, and ge neral-purpose i/o. when sci2 or iic1 modules are enabled, the pin direction will be controlle d by the module or function. port c has high current output drivers. port c pins are available as genera l-purpose i/o pins contro lled by the port c data (ptcd), data direction (ptcdd), pullup enable (ptcpe), and slew rate control (ptcse) registers. refer to section 6.4, ?parallel i/o controls ,? for more information about general-purpose i/o control. when the sci2 module is enabled, ptc0 serves as the sci2 module?s transmit pin (txd2) and ptc1 serves as the receive pin (rxd2). refer to chapter 11, ?serial communications interface (s08sciv1) ,? for more information about using ptc0 and ptc1 as sci pins when the iic module is enabled, pt c2 serves as the iic modules?s se rial data input/ output pin (sda1) and ptc3 serves as the cl ock pin (scl1). refer to chapter 13, ?inter-integrated circuit (s08iicv1) ,? for more information about using ptc2 and ptc3 as iic pins. port b bit 7654321bit 0 mcu pin: ptb7/ ad1p7 ptb6/ ad1p6 ptb5/ ad1p5 ptb4/ ad1p4 ptb3/ ad1p3 ptb2/ ad1p2 ptb1/ ad1p1 ptb0/ ad1p0 port c bit 7653321bit 0 mcu pin: ptc7 ptc6 ptc5 ptc4 ptc3/ scl1 ptc2/ sda1 ptc1/ rxd2 ptc0/ txd2
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 85 6.3.4 port d, tpm1 and tpm2 figure 6-5. port d pin names port d is an 8-bit port shared with the two tpm modules, tpm1 and tpm2, and general-purpose i/o. when the tpm1 or tpm2 modules are enabled in output compare or input capt ure modes of operation, the pin direction will be co ntrolled by the module function. port d pins are available as general-purpose i/o pins controlled by the port d data (ptdd), data direction (ptddd), pullup enable (ptdpe), and slew rate control (ptdse) registers. refer to section 6.4, ?parallel i/o controls ? for more information about general-purpose i/o control. the tpm2 module can be configured to use ptd7?ptd3 as either input capture, output compare, pwm, or external clock input pi ns (ptd3 only). refer to chapter 10, ?timer/pwm (s08tpmv1) ? for more information about using pt d7?ptd3 as timer pins. the tpm1 module can be configured to use ptd2?ptd0 as either input capture, output compare, pwm, or external clock input pi ns (ptd0 only). refer to chapter 10, ?timer/pwm (s08tpmv1) ? for more information about using pt d2?ptd0 as timer pins. 6.3.5 port e, sci1, and spi figure 6-6. port e pin names port e is an 8-bit port shared with the sci1 modul e, spi1 module, and general- purpose i/o. when the sci or spi modules are enabled, the pin directi on will be controlled by the module function. port e pins are available as genera l-purpose i/o pins controlled by the port e data (pted), data direction (ptedd), pullup enable (ptepe), and slew ra te control (ptese) registers. refer to section 6.4, ?parallel i/o controls ? for more information about general-purpose i/o control. when the sci1 module is enabled, pte0 serves as the sci1 module?s transmit pin (txd1) and pte1 serves as the receive pin (rxd1). refer to chapter 11, ?serial communications interface (s08sciv1) ? for more information about using pte0 and pte1 as sci pins. when the spi module is enabled, pte2 serves as the spi module?s slave select pin (ss1 ), pte3 serves as the master-in slave-out pin (miso1), pte4 serves as the master-out slave-in pin (mosi1), and pte5 serves as the spi clock pin (spsck1). refer to chapter 12, ?serial peripheral interface (s08spiv3) for more information about using pte5?pte2 as spi pins. port d bit 7654321bit 0 mcu pin: ptd7/ tpm2ch4 ptd6/ tpm2ch3 ptd5/ tpm2ch2 ptd4/ tpm2ch1 ptd3/ tpm2ch0 ptd2/ tpm1ch2 ptd1/ tpm1ch1 ptd0/ tpm1ch0 port e bit 7654321bit 0 mcu pin: pte7 pte6 pte5/ spsck1 pte4/ mosi1 pte3/ miso1 pte2/ ss 1 pte1/ rxd1 pte0/ txd1
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 86 freescale semiconductor 6.3.6 port f and high-current drivers figure 6-7. port f pin names port f is an 8-bit port general-purpos e i/o that is not shared with any peripheral module. port f has high current output drivers. port f pins are available as general-purpose i/o pins controlled by the port f data (ptfd), data direction (ptfdd), pullup enable (ptfpe), and slew ra te control (ptfse) registers. refer to section 6.4, ?parallel i/o controls ? for more information about general-purpose i/o control. 6.3.7 port g, bkgd/ms, and oscillator figure 6-8. port g pin names port g is an 8-bit port which is shared among the background/mode select function, oscillator, and general-purpose i/o. when the backgr ound/mode select function or oscillator is enab led, the pin direction will be controlled by the module function. port g pins are available as general-purpose i/o pins controlled by the port g data (ptgd), data direction (ptgdd), pullup enable (ptgpe), and slew rate control (ptgse) registers. refer to section 6.4, ?parallel i/o controls ? for more information about general-purpose i/o control. the internal pullup for ptg0 is enabled when the b ackground/mode select functi on is enabled, regardless of the state of ptgpe0. during rese t, the bkgd/ms pin functions as a mode select pin. after the mcu is out of reset, the bkgd/ms pin becomes the background comm unications input/output pin. the ptg0 can be configured to be a ge neral-purpose output pin. refer to chapter 3, ?modes of operation ?, chapter 5, ?resets, interrupts, and system configuration ? , and chapter 15, ?development support ? for more information about using this pin. the icg module can be configured to use ptg2?ptg1 ports as crystal os cillator or external clock pins. refer to chapter 13, ?inter-integra ted circuit (s08iicv1) ? for more information about using these pins as oscillator pins. port f bit 7654321bit 0 mcu pin: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 port g bit 7654321bit 0 mcu pin: ptg7 ptg6 ptg5 ptg4 ptg3 ptg2/ extal ptg1/ xtal ptg0/ bkgd/ms
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 87 6.4 parallel i/o controls provided no on-chip peripheral is cont rolling a port pin, the pins operate as general-purpose i/o pins that are accessed and controlled by a data register (ptxd), a data direction register (ptxdd), a pullup enable register (ptxpe), and a slew rate control register (ptxse) where x is a, b, c, d, e, f, or g. reads of the data register return the pin value (if ptxd dn = 0) or the contents of the port data register (if ptxddn = 1). writes to the port data re gister are latched into the port regi ster whether the pi n is controlled by an on-chip peripheral or the pin is configured as an input. if the co rresponding pin is not controlled by a peripheral and is configured as an output, this level will be driven out the port pin. 6.4.1 data direction control the data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. each port pin has a data directi on control bit. when ptxddn = 0, the corresponding pin is an input and reads of ptxd return the pin value. when ptxddn = 1, the corresponding pin is an output and read s of ptxd return the last value written to the port data register. when a peripheral module or system function is in c ontrol of a port pin, the data direction control still controls what is returned for reads of the port da ta register, even though th e peripheral system has overriding control of the actual pin direction. for the mc9s08gbxxa/gtxxa mcu, reads of ptg0/bkgd/ms will return the value on the output pin. it is a good programming practice to wr ite to the port data register before changing the direction of a port pin to become an output. this ensures that the pin wi ll not be driven momentarily with an old data value that happened to be in the port data register. 6.4.2 internal pullup control an internal pullup device can be enabled for each port pin that is configured as an input (ptxddn = 0). the pullup device is available for a pe ripheral module to use, provided the peripheral is enabled and is an input function as long as the ptxddn = 0. for the four configurable kbi module inputs on pta7?p ta4, when a pin is configured to detect rising edges, the port pullup enable associ ated with the pin (ptapen) selects a pulldown rather than a pullup device. 6.4.3 slew rate control slew rate control can be enabled fo r each port pin that is configured as an output (ptxddn = 1) or if a peripheral module is enable d and its function is an output. not all peripheral m odules? outputs have slew rate control; refer to chapter 2, ?pins and connections ? for more information about which pins have slew rate control.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 88 freescale semiconductor 6.5 stop modes depending on the stop mode, i/o functions differently as the result of executing a stop instruction. an explanation of i/o behavior fo r the various stop modes follows: ? when the mcu enters stop1 mode, all internal registers including general-purpose i/o control and data registers are powered down. all of the gene ral-purpose i/o pins assu me their reset state: output buffers and pullups turned off. upon exit fr om stop1, all i/o must be initialized as if the mcu had been reset. ? when the mcu enters stop2 mode, the internal re gisters are powered down as in stop1 but the i/o pin states are latched and held. for example, a por t pin that is an output driving low continues to function as an output driving low even though its asso ciated data direction an d output data registers are powered down internally. upon exit from stop2, th e pins continue to hold their states until a 1 is written to the ppdack bit. to avoid discontinuity in the pin st ate following exit from stop2, the user must restore the port control and data registers to the values they he ld before entering stop2. these values can be stored in ram before ente ring stop2 because the ra m is maintained during stop2. ? in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user. 6.6 parallel i/o registers and control bits this section provides information about all registers and contro l bits associated with the parallel i/o ports. refer to tables in chapter 4, ?memory ? for the absolute address assignments for all parallel i/o registers. this section refers to registers a nd control bits only by thei r names. a freescale-provi ded equate or header file normally is used to translate these na mes into the appropriate absolute addresses. 6.6.1 port a registers (ptad, ptape, ptase, and ptadd) port a includes eight pins shared between general-purpose i/o and the kbi module. port a pins used as general-purpose i/o pins are controlled by the port a da ta (ptad), data directi on (ptadd), pullup enable (ptape), and slew rate control (ptase) registers. if the kbi takes control of a port a pin, the correspondi ng ptase bit is ignored si nce the pin functions as an input. as long as ptadd is 0, the ptape controls the pullup enable for the kbi function. reads of ptad will return the logic value of the corresponding pin, provided ptadd is 0.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 89 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w reset00000000 figure 6-9. port a data register (ptad) table 6-1. ptad field descriptions field description 7:0 ptad[7:0] port a data register bits ? for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port a pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins be cause reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 w reset00000000 figure 6-10. pullup enable for port a (ptape) table 6-2. ptape field descriptions field description 7:0 ptape[7:0] pullup enable for port a bits ? for port a pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled provided the corresponding ptaddn is 0. for port a pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. when any of bits 7 through 4 of port a are enabled as kbi inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 internal pullup device disabled. 1 internal pullup device enabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 90 freescale semiconductor 76543210 r ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 w reset00000000 figure 6-11. slew rate control enable for port a (ptase) table 6-3. ptase field descriptions field description 7:0 ptase[7:0] slew rate control enable for port a bits ? for port a pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enab led. for port a pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 w reset00000000 figure 6-12. data direction for port a (ptadd) table 6-4. ptadd field descriptions field description 7:0 ptadd[7:0] data direction for port a bits ? these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 91 6.6.2 port b registers (ptbd, ptbpe, ptbse, and ptbdd) port b includes eight general-purpose i/o pins that share with the at d function. port b pins used as general-purpose i/o pins are controlled by the port b data (ptbd), da ta direction (ptbdd), pullup enable (ptbpe), and slew rate control (ptbse) registers. if the atd takes control of a port b pin, the corr esponding ptbdd, ptbse, and ptbpe bits are ignored. when a port b pin is being used as an atd pin, read s of ptbd will return a 0 of the corresponding pin, provided ptbdd is 0. 76543210 r ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 w r e s e t00000000 figure 6-13. port b data register (ptbd) table 6-5. ptbd field descriptions field description 7:0 ptbd[7:0] port b data register bits ? for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port b pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not dr iven out on the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 w r e s e t00000000 figure 6-14. pullup enable for port b (ptbpe) table 6-6. ptbpe field descriptions field description 7:0 ptbpe[7:0] pullup enable for port b bits ? for port b pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port b pins that are configured as outputs, th ese bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 92 freescale semiconductor 76543210 r ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 w r e s e t00000000 figure 6-15. data direction for port a (ptbse) table 6-7. ptbse field descriptions field description 7:0 ptbse[7:0] slew rate control enable for port b bits ? for port b pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enab led. for port b pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 w r e s e t00000000 figure 6-16. data direction for port b (ptbdd) table 6-8. ptbdd field descriptions field description 7:0 ptbdd[7:0] data direction for port b bits ? these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 93 6.6.3 port c registers (ptcd, ptcpe, ptcse, and ptcdd) port c includes eight general-purpose i/o pins that sh are with the sci2 and iic modules. port c pins used as general-purpose i/o pins are controlled by the por t c data (ptcd), data direction (ptcdd), pullup enable (ptcpe), and slew ra te control (ptcse) registers. if the sci2 takes control of a port c pin, the corres ponding ptcdd bit is ignore d. ptcse can be used to provide slew rate on the sci2 transmit pin, tx d2. ptcpe can be used, provided the corresponding ptcdd bit is 0, to provide a pullup de vice on the sci2 receive pin, rxd2. if the iic takes control of a port c pin, the corres ponding ptcdd bit is ignore d. ptcse can be used to provide slew rate on the iic serial data pin (sda1), when in output mode and the iic clock pin (scl1). ptcpe can be used, provided the corresponding ptcdd bit is 0, to provide a pullup device on the iic serial data pin, when in receive mode. reads of ptcd will return the logic value of the corresponding pin, provided ptcdd is 0. 76543210 r ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 w r e s e t00000000 figure 6-17. port c data register (ptcd) table 6-9. ptcd field descriptions field description 7:0 ptcd[7:0] port c data register bits ? for port c pins that are inputs, reads return the logic level on the pin. for port c pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port c pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 94 freescale semiconductor 76543210 r ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset00000000 figure 6-18. pullup enable for port c (ptcpe) table 6-10. ptcpe field descriptions field description 7:0 ptcpe[7:0] pullup enable for port c bits ? for port c pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port c pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled. 76543210 r ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 w reset00000000 figure 6-19. slew rate control enable for port c (ptcse) table 6-11. ptcse field descriptions field description 7:0 ptcse[7:0] slew rate control enable for port c bits ? for port c pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enab led. for port b pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset00000000 figure 6-20. data direction for port c (ptcdd) table 6-12. ptcdd field descriptions field description 7:0 ptcdd[7:0] data direction for port c bits ? these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 95 6.6.4 port d registers (ptdd, ptdpe, ptdse, and ptddd) port d includes eight pins shared between general-purpose i/o, tpm1, and tpm2. port d pins used as general-purpose i/o pins are controlled by the port d da ta (ptdd), data directi on (ptddd), pullup enable (ptdpe), and slew rate control (ptdse) registers. if a tpm takes control of a port d pin, the corres ponding ptddd bit is ignored. when the tpm is in output compare mode, the correspondi ng ptdse can be used to provide slew rate on the pin. when the tpm is in input captur e mode, the corresponding ptdpe can be used, provi ded the corresponding ptddd bit is 0, to provide a pullup device on the pin. reads of ptdd will return the logic value of the corresponding pin, provided ptddd is 0. 76543210 r ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 w r e s e t00000000 figure 6-21. port d data register (ptdd) table 6-13. ptdd field descriptions field description 7:0 ptdd[7:0] port d data register bits ? for port d pins that are inputs, reads return the logic level on the pin. for port d pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port d pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptdd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 w reset00000000 figure 6-22. pullup enable for port d (ptdpe) table 6-14. ptdpe field descriptions field description 7:0 ptdpe[7:0] pullup enable for port d bits ? for port d pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port d pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 96 freescale semiconductor 76543210 r ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 w reset00000000 figure 6-23. slew rate control enable for port d (ptdse) table 6-15. ptdse field descriptions field description 7:0 ptdse[7:0] slew rate control enable for port d bits ? for port d pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are en abled. for port d pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 w reset00000000 figure 6-24. data direction for port d (ptddd) table 6-16. ptddd field descriptions field description 7:0 ptddd[7:0] data direction for port d bits ? these read/write bits control the direction of port d pins and what is read for ptdd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port d bit n and ptdd reads return the contents of ptddn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 97 6.6.5 port e registers (pted, ptepe, ptese, and ptedd) port e includes eight general-purpose i/o pins that share with the sci1 and spi modules. port e pins used as general-purpose i/o pins are controlled by the por t e data (pted), data direction (ptedd), pullup enable (ptepe), and slew rate control (ptese) registers. if the sci1 takes control of a por t e pin, the corresponding ptedd bit is ignored. ptese can be used to provide slew rate on the sci1 transmit pin, txd1. ptepe can be use d, provided the corresponding ptedd bit is 0, to provide a pullup devi ce on the sci1 receive pin, rxd1. if the spi takes control of a port e pin, the corres ponding ptedd bit is ignored. ptese can be used to provide slew rate on the spi serial output pin (mosi1 or miso1) and serial clock pin (spsck1) depending on the spi operational mode. ptepe can be used, provided the corresponding ptedd bit is 0, to provide a pullup device on the spi serial input pins (mosi1 or miso1) and slave select pin (ss1 ) depending on the spi operational mode. reads of pted will return the logic value of the corresponding pin, provided ptedd is 0. 76543210 r pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 w r e s e t00000000 figure 6-25. port e data register (pted) table 6-17. pted field descriptions field description 7:0 pted[7:0] port e data register bits ? for port e pins that are inputs, reads return the logic level on the pin. for port e pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits in this register. for port e pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces pted to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 98 freescale semiconductor 76543210 r ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 w r e s e t00000000 figure 6-26. pullup enable for port e (ptepe) table 6-18. ptepe field descriptions field description 7:0 ptepe[7:0] pullup enable for port e bits ? for port e pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port e pins that are configured as outputs, th ese bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled. 76543210 r ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 w r e s e t00000000 figure 6-27. slew rate control enable for port e (ptese) table 6-19. ptese field descriptions field description 7:0 ptese[7:0] slew rate control enable for port e bits ? for port e pins that are outputs, these read/write control bits determine whether the slew rate contro lled outputs are enabled. for port e pins that are conf igured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 w r e s e t00000000 figure 6-28. data direction for port e (ptedd) table 6-20. ptedd field descriptions field description 7:0 ptedd[7:0] data direction for port e bits ? these read/write bits control the direction of port e pins and what is read for pted reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port e bit n and pted reads return the contents of ptedn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 99 6.6.6 port f registers (ptfd, ptfpe, ptfse, and ptfdd) port f includes eight general-purpos e i/o pins that are not shared with any peripheral module. port f pins used as general-purpose i/o pins are controlled by the port f data (ptfd), data direction (ptfdd), pullup enable (ptfpe), and slew ra te control (ptfse) registers. 76543210 r ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 w reset00000000 figure 6-29. port ptf data register (ptfd) table 6-21. ptfd field descriptions field description 7:0 ptfd[7:0] port ptf data register bits ? for port f pins that are inputs, reads return the logic level on the pin. for port f pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port f pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptfd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 w r e s e t00000000 figure 6-30. pullup enable for port f (ptfpe) table 6-22. ptfpe field descriptions field description 7:0 ptfpe[7:0] pullup enable for port f bits ? for port f pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port f pins that ar e configured as outputs, t hese bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 100 freescale semiconductor 6.6.7 port g registers (ptgd, ptgpe, ptgse, and ptgdd) port g includes eight general-purpose i/o pins that are shar ed with bkgd/ms functi on and the oscillator or external clock pins. port g pi ns used as general-purpose i/o pins are controlled by the port g data (ptgd), data direction (ptgdd), pullup enable (ptg pe), and slew rate control (ptgse) registers. port pin ptg0, while in reset, defaults to the bkgd /ms pin. after the mcu is out of reset, ptg0 can be configured to be a general-purpos e output pin. when bkgd/ms takes control of ptg0, the corresponding ptgdd, ptgpe, and ptg pse bits are ignored. port pins ptg1 and ptg2 can be configured to be os cillator or external clock pins. when the oscillator takes control of a port g pin, the corresponding ptgd, ptgdd, ptgse, and ptgpe bits are ignored. reads of ptgd will return the logic value of the corresponding pin, provided ptgdd is 0. 76543210 r ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 w r e s e t00000000 figure 6-31. slew rate control enable for port f (ptfse) table 6-23. ptfse field descriptions field description 7:0 ptfse[7:0] slew rate control enable for port f bits ? for port f pins that are outpu ts, these read/write control bits determine whether the slew rate controlled outputs are enab led. for port f pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 w reset00000000 figure 6-32. data direction for port f (ptfdd) table 6-24. ptfdd field descriptions field description 7:0 ptfdd[7:0] data direction for port f bits ? these read/write bits control the directio n of port f pins and what is read for ptfd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port f bit n and ptfd reads return the contents of ptfdn.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 freescale semiconductor 101 76543210 r ptgd7 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 w r e s e t00000000 figure 6-33. port ptg data register (ptgd) table 6-25. ptgd field descriptions field description 7:0 ptgd[7:0] port ptg data register bits ? for port g pins that are inputs, reads return the logic level on the pin. for port g pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port g pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptgd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptgpe7 ptgpe6 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 w r e s e t00000000 figure 6-34. pullup enable for port g (ptgpe) table 6-26. ptgpe field descriptions field description 7:0 ptgpe[7:0] pullup enable for port g bits ? for port g pins that are inputs, thes e read/write control bits determine whether internal pullup devices are enabled. for port g pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 internal pullup device disabled. 1 internal pullup device enabled.
chapter 6 parallel input/output mc9s08gb60a data sheet, rev. 2 102 freescale semiconductor 76543210 r ptgse7 ptgse6 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 w r e s e t00000000 figure 6-35. slew rate control enable for port g (ptgse) table 6-27. ptgse field descriptions field description 7:0 ptgse[7:0] slew rate control enable for port g bits ? for port g pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enab led. for port g pins that are configured as inputs, these bits are ignored. 0 slew rate control disabled. 1 slew rate control enabled. 76543210 r ptgdd7 ptgdd6 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 w r e s e t00000000 figure 6-36. data direction for port g (ptgdd) table 6-28. ptgdd field descriptions field description 7:0 ptgdd[7:0] data direction for port g bits ? these read/write bits control the directio n of port g pins and what is read for ptgd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port g bit n and ptgd reads return the contents of ptgdn.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 103 chapter 7 internal clock generator (s08icgv2) the mc9s08gbxxa/gtxxa microcontroller provides one internal cl ock generation (icg) module to create the system bus frequency. all functions described in this section are available on the mc9s08gbxxa/gtxxa microcontroller. the extal and xtal pins share port g bits 2 and 1, respectively. analog supply lines v dda and v ssa are internally derived from the mcu?s v dd and v ss pins. electrical parametric data for the icg may be found in appendix a, ?electrical characteristics .? figure 7-1. system clock distribution diagram note freescale semiconductor recommends that flash location $ffbe be reserved to store a nonvolatile ve rsion of icgtrm. this will allow debugger and programmer vendors to perform a manual trim operation and store the resultant icgtrm value for users to access at a later time. atd has min and max frequency requirements. see chapter 1, ?device overview ? and appendix a, ?electrical characteristics . flash has frequency requirements for program and erase operation. see appendix a, ?electrical characteristics . * icglclk is the alternate bdc clock source for the mc9s08gbxxa/gtxxa. tpm1 tpm2 iic1 sci1 sci2 spi1 bdc cpu atd1 ram flash icg icgout 2 ffe system logic busclk icglclk* control fixed freq clock (xclk) icgerclk rti 2
chapter 7 internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 104 freescale semiconductor figure 7-2. block diagram highlighting icg module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 105 7.1 introduction figure 7-3 is a top-level diagram that s hows the functional organization of the internal clock generation (icg) module. this section includes a ge neral description and a feature list. figure 7-3. icg block diagram the icg provides multiple options for clock sources. this offers a user great flexibility when making choices between cost, prec ision, current draw, and performance. as seen in figure 7-3 , the icg consists of four functional blocks. each of these is briefly described here and then in more detail in a later section. ? oscillator block ? the oscillator block provides means for connecting an external crystal or resonator. two frequency ranges are software sel ectable to allow optimal startup and stability. alternatively, the oscillator block ca n be used to route an external squa re wave to the system clock. external sources can provide a very precise cloc k source. the oscillator is capable of being configured for low power mode or hi gh amplitude mode as selected by hgo. ? internal reference generator ? the internal reference generator consists of two controlled clock sources. one is designed to be a pproximately 8 mhz and can be selected as a local clock for the background debug controller. the other internal re ference clock source is typically 243 khz and can be trimmed for finer accuracy via software when a precise ti med event is input to the mcu. this provides a highly reliable, low-cost clock source. ? frequency-locked loop ? a frequency-locked loop (fll) st age takes either the internal or external clock source and multiplies it to a higher freque ncy. status bits provi de information when the circuit has achieved lock and when it falls out of lock. additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. oscillator (osc) frequency internal extal xtal reference generators clock select 8 mhz irg loss of lock and clock detector locked loop (fll) fixed clock select icgout typ 243 khz rg icglclk icg ffe v dda v ssa (see note 2) (see note 2) dco with external ref select ref select local clock for optional use with bdc output clock select icgdclk /r icgerclk icgirclk notes: 1. see table 7-1 for specific use of icgout, ffe, icglclk, icgerclk 2. not all hcs08 microcontrollers have unique supply pins for the icg. see the device pin assignments in chapter 2, ?pins and connections for specifics.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 106 freescale semiconductor ? clock select block ? the clock select block provides several switch options for connecting different clock sources to the system clock tree. icgdclk is the multip lied clock frequency out of the fll, icgerclk is the reference clock fre quency from the crystal or external clock source, and ffe (fixed frequency enable) is a control signal used to control the system fixed frequency clock (xclk). icglclk is the clock source for the background debug controller (bdc). the module is intended to be very us er friendly with many of the featur es occurring automatically without user intervention. to quickly configure the module, go to section 7.4, ?initiali zation/application information ? and pick an example that best suits the application needs. 7.1.1 features features of the icg and clock distribution system: ? several options for the primary clock source allow a wide range of cost, frequency, and precision choices: ? 32 khz?100 khz crystal or resonator ? 1 mhz?16 mhz crystal or resonator ? external clock ? internal reference generator ? defaults to self-clocked mode to minimize startup delays ? frequency-locked loop (fll) generates 8 m hz to 40 mhz (for bus rates up to 20 mhz) ? uses external or internal clock as reference frequency ? automatic lockout of non-running clock sources ? reset or interrupt on loss of clock or loss of fll lock ? digitally-controlled oscillator (dco) preserves previous fre quency settings, allowing fast frequency lock when re covering from stop3 mode ? dco will maintain operating frequency during a loss or removal of reference clock ? post-fll divider selects 1 of 8 bus rate divisors (/1 through /128) ? separate self-clocked s ource for real-time interrupt ? trimmable internal clock source supports sci communications without additional external components ? automatic fll engagement after lock is acquired ? selectable low-power/high-gain oscillator modes
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 107 7.1.2 modes of operation this is a high-level description only. detailed descriptions of operating modes are contained in section 7.3, ?functional description .? ? mode 1 ? off the output clock, icgout, is static. this mode may be entered when the stop instruction is executed. ? mode 2 ? self-clocked (scm) default mode of operation that is entered out of reset. the icg?s fll is open loop a nd the digitally controlled oscillator (dco) is free running at a frequency set by the filter bits. ? mode 3 ? fll engaged internal (fei) in this mode, the icg?s fll is used to create frequencies that are progr ammable multiples of the internal reference clock. ? fll engaged internal unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency. ? fll engaged internal locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. ? mode 4 ? fll bypassed external (fbe) in this mode, the icg is configured to bypass the fll and use an ex ternal clock as the clock source. ? mode 5 ? fll engaged external (fee) the icg?s fll is used to generate frequencies that are programmable multiples of the external clock reference. ? fll engaged external unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency. ? fll engaged external locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. 7.2 oscillator pins the oscillator pins are used to provide an external clock source for the mcu. 7.2.1 extal? external refere nce clock / oscillator input if upon the first write to icgc1, either fee mode or fbe mode is selected, this pin functions as either the external clock input or the input of the oscillator circuit as determined by refs. if upon the first write to icgc1, either fei mode or scm mode is selected, this pin is not used by the icg. 7.2.2 xtal? oscillator output if upon the first write to icgc1, either fee mode or fb e mode is selected, this pin functions as the output of the oscillator circuit. if upon the first write to ic gc1, either fei mode or sc m mode is selected, this
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 108 freescale semiconductor pin is not used by the icg. the osci llator is capable of being configured to provide a higher amplitude output for improved noise immunity. this mode of operation is selected by hgo = 1. 7.2.3 external clock connections if an external clock is used, then the pins are connected as shown in figure 7-4 . figure 7-4. external clock connections 7.2.4 external crystal/resonator connections if an external crystal/resonator frequency reference is used, then th e pins are connected as shown in figure 7-5 . recommended component values are listed in appendix a, ?electri cal characteristics .? figure 7-5. external frequency reference connection icg xtal extal v ss clock input not connected icg extal xtal v ss c 1 c 2 crystal or resonator r f r s
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 109 7.3 functional description this section provides a func tional description of each of the five operating modes of the icg. also covered are the loss of clock and loss of lock errors and requirements for entry into each mode. the icg is very flexible, and in some conf igurations, it is possible to exceed certain clock speci fications. when using the fll, configure the icg so that th e frequency of icgdclk does not exce ed its maximum value to ensure proper mcu operation. 7.3.1 off mode (off) normally when the cpu enters stop mode, the icg will cease all clock activity and is in the off state. however there are two cases to consider when cloc k activity continues while the cpu is in stop mode. 7.3.1.1 bdm active when the bdm is enabled (enbdm = 1), the icg c ontinues activity as originally programmed. this allows access to memory and control registers via the bdc. 7.3.1.2 oscsten bit set when the oscillator is enabled in stop mode (oscsten = 1), the indivi dual clock generators are enabled but the clock feed to the rest of the mcu is turned off. this option is provided to avoid long oscillator startup times if necessary, or to run the rti from the oscillator during stop3. 7.3.1.3 stop/off mode recovery upon the cpu exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. if fee is select ed, the icg will source the internal reference until th e external clock is stable. if fbe is selected, the icg will wait for the external clock to stabilize before enabling icgout. upon the cpu exiting stop mode due to a reset, the previously set icg control bits are ignored and the default reset values applied. therefore the icg will exit stop in scm mode configured for an approximately 8 mhz dco output (4 mhz bus clock) with trim value maintained. if using a crystal, 4096 clocks are detected prior to engaging icgerclk. this is incorporated in crystal start-up time. 7.3.2 self-clocked mode (scm) self-clocked mode (scm) is the de fault mode of operation and is en tered when any of the following conditions occur: ? after any reset. ? exiting from off mode when clks does not e qual 10. if clks = x1, the icg enters this state temporarily until the dco is stable (dcos = 1). ? clks bits are written from x1 to 00. ? clks = 1x and icgerclk is not detected (both ercs = 0 and locs = 1).
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 110 freescale semiconductor in this state, the fll loop is open. the dco is on, a nd the output clock signal ic gout frequency is given by f icgdclk / r. the icgdclk frequency can be varied from 8 mhz to 40 mhz by writing a new value into the filter registers (icgfltu and icgfltl). this is the only mode in which the filter registers can be written. if this mode is ente red due to a reset, f icgdclk will default to f self_reset which is nominally 8 mhz. if this mode is entered from fll engaged internal, f icgdclk will maintain the previous frequency. if this mode is entered from fll engaged external (either by progr amming clks or due to a loss of external reference clock), f icgdclk will maintain the previous fr equency, but icgout will doubl e if the fll was unlocked. if this mode is entered from off mode, f icgdclk will be equal to the frequency of icgdclk before entering off mode. if clks bits are set to 01 or 11 co ming out of the off state, the icg enters this mode until icgdclk is stable as determ ined by the dcos bit. once icgdclk is considered stable, the icg automatically closes the loop by switching to fll enga ged (internal or external) as selected by the clks bits. figure 7-6. detailed frequency-locked loop block diagram reference divider (/7) rfd clkst subtractor loop filter digitally controlled oscillator clock icgout icg2dclk reset and interrupt irq fll analog select circuit lols pulse counter mfd frequency- icgerclk locs lock and detector lock control lolre locre reset reduced frequency divider (r) loss of clock icgif ercs icgdclk loop (fll) digital flt counter enable locked overflow 1x 2x icgirclk clkst dcos range range clks locd
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 111 7.3.3 fll engaged, internal clock (fei) mode fll engaged internal (fei) is entered wh en any of the following conditions occur: ? clks bits are written to 01 ? the dco clock stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 01 in fll engaged internal mode, th e reference clock is derived from the internal reference clock icgirclk, and the fll loop will attempt to lock the icgdclk frequency to the desired value, as selected by the mfd bits. 7.3.3.1 fll engaged internal unlocked fei unlocked is a temporary state that is ente red when fei is entere d and the count error ( n) output from the subtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detect or to detect the lock condition. in this state the output clock signa l icgout frequency is given by f icgdclk / r. 7.3.3.2 fll engaged internal locked fll engaged internal locked is entered from fei unloc ked when the count error ( n), which comes from the subtractor, is less than n lock (max) and greater than nlock (min) for a given number of samples, as required by the lock detector to de tect the lock condition. the output clock signal icgout frequency is given by f icgdclk / r. in fei locked, the filter value is only updated once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 7.3.4 fll bypassed, external clock (fbe) mode fll bypassed external (fbe) is entered when any of the following conditions occur: ? from scm when clks = 10 and ercs is high ? when clks = 10, ercs = 1 upon entering off mode, and off is then exited ? from fll engaged external mode if a loss of dco clock occurs and the exte rnal reference is still valid (both locs = 1 and ercs = 1) in this state, the dco and irg are off and the referenc e clock is derived from th e external reference clock, icgerclk. the output clock signal icgout frequency is given by f icgerclk / r. if an external clock source is used (refs = 0), then the input frequenc y on the extal pin can be anywhere in the range 0 mhz to 40 mhz. if a crystal or resonator is used (refs = 1), then frequency range is either low for range = 0 or high for range = 1. 7.3.5 fll engaged, external clock (fee) mode the fll engaged external (fee) mode is entered when any of the following conditions occur: ? clks = 11 and ercs and dcos are both high. ? the dco stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 11.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 112 freescale semiconductor in fee mode, the reference clock is derived from the external refe rence clock icgerclk, and the fll loop will attempt to lock the icgdclk frequency to th e desired value, as selected by the mfd bits. to run in fee mode, there must be a working 32 khz ?100 khz or 2 mhz?10 mhz external clock source. the maximum external clock frequency is limited to 10 mhz in fee mode to prevent over-clocking the dco. the minimum multiplier for the fll, from table 7-7 , is 4. because 4 x 10 mhz is 40 mhz, which is the operational limit of the dco, the reference clock cannot be any faster than 10 mhz. 7.3.5.1 fll engaged external unlocked fee unlocked is entered when fee is entered and the count error ( n) output from the s ubtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detect or to detect the lock condition. in this state, the pulse counter, s ubtractor, digital loop filt er, and dco form a closed loop and attempt to lock it according to their operational descriptions later in this secti on. upon entering this state and until the fll becomes locked, the output cloc k signal icgout freque ncy is given by f icgdclk / (2 r). this extra divide by two prevents frequency overshoots dur ing the initial locking process from exceeding chip-level maximum freque ncy specifications. as s oon as the fll has locked, if an unexpected loss of lock causes it to re-enter the unlocked state while the icg remains in fee mode, the output clock signal icgout frequency is given by f icgdclk / r. 7.3.5.2 fll engaged external locked fee locked is entered from fee unlocked when the count error ( n) is less than n lock (max) and greater than n lock (min) for a given number of samples, as requi red by the lock detector to detect the lock condition. the output clock signal ic gout frequency is given by f icgdclk /r. in fll engaged external locked, the filter value is only updated once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 7.3.6 fll lock and loss-of-lock detection to determine the fll locked and loss-of-lock condi tions, the pulse counter c ounts the pulses of the dco for one comparison cycle (see table 7-2 for explanation of a comparison cycle) and passes this number to the subtractor. the subtr actor compares this value to the valu e in mfd and produces a count error, n. to achieve locked status, n must be between n lock (min) and n lock (max). as soon as the fll has locked, n must stay between n unlock (min) and n unlock (max) to remain locked. if n goes outside this range unexpectedly, the lols status bit is set and remains set until acknowledged or until the mcu is reset. lols is cleared by reading icgs1 then writing 1 to icgif (lolre = 0), or by a loss-of-lock induced reset (lolre = 1), or by any mcu reset. if the icg enters the off state due to stop mode when enbdm = oscsten = 0, the fll loses locked status (lock is cleared), but lols remains unchanged because this is not an unexpected loss-of-lock condition. though it would be unusual, if enbdm is cleared to 0 while th e mcu is in stop, the icg enters
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 113 the off state. because this is an unexpected stopping of clocks, lols will be set when the mcu wakes up from stop. expected loss of lock occurs when the mfd or clks bits are changed or in fei mode only, when the trim bits are changed. in these cases, the lock bit will be cleared until the fll regains lock, but the lols will not be set. 7.3.7 fll loss-of-clock detection the reference clock and the dco clock are monitored under different conditions (see table 7-1 ). provided the reference frequency is being monitored, ercs = 1 indicates that the reference clock meets minimum frequency requirements. when the re ference and/or dc o clock(s) are being monitored, if either one falls below a certain frequency, f lor and f lod , respectively, the locs status bit wi ll be set to indicate the error. locs will remain set until it is cleared by software or until the mcu is reset. locs is cleared by reading icgs1 then writing 1 to icgif (lo cre = 0), or by a loss-of-clock indu ced reset (locre = 1), or by any mcu reset. if the icg is in fee, a loss of reference clock causes the icg to enter scm, and a loss of dco clock causes the icg to enter fbe mode. if the icg is in fbe m ode, a loss of reference clock will cause the icg to enter scm. in each case, the clkst and clks bits will be automatically changed to reflect the new state. a loss of clock will also cause a loss of lock when in fee or fei modes. b ecause the method of clearing the locs and lols bits is the same, this would onl y be an issue in the unlikely case that lolre = 1 and locre = 0. in this case, the interrupt would be overridden by the reset for the loss of lock. table 7-1. clock monitoring (when locd = 0) mode clks refst ercs external reference clock monitored? dco clock monitored? off 0x or 11 x forced low no no 10 0 forced low no no 10 1 real-time 1 1 if enable is high (waiting for external crystal start-up after exiting stop). ye s (1) no scm (clkst = 00) 0x x forced low no ye s 2 2 dco clock will not be monitored until dcos = 1 upon enteri ng scm from off or fll bypassed external mode. 10 0 forced high no ye s (2) 10 1 real-time yes ye s (2) 11 x real-time yes ye s (2) fei (clkst = 01) 0x x forced low no yes 11 x real-time yes yes fbe (clkst = 10) 10 0 forced high no no 10 1 real-time yes no fee (clkst = 11) 11 x real-time yes yes
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 114 freescale semiconductor 7.3.8 clock mode requirements a clock mode is requested by writ ing to clks1:clks0 and the actu al clock mode is indicated by clkst1:clkst0. provided minimum c onditions are met, the status shown in clkst1:clkst0 should be the same as the reques ted mode in clks1:clks0. table 7-2 shows the relationship between clks, clkst, and icgout. it also shows the conditions for clks = clkst or the reason clks clkst. note if a crystal will be used before the next reset, then be sure to set refs = 1 and clks = 1x on the first write to the ic gc1 register. failure to do so will result in ?locking? refs = 0, which will prevent the oscillator amplifier from being enabled until the next reset occurs. table 7-2. icg state table actual mode (clkst) desired mode (clks) range reference frequency (f reference ) comparison cycle time icgout conditions 1 for clks = clkst 1 clkst will not update immediatel y after a write to clks. seve ral bus cycles are required befo re clkst update s to the new value. reason clks1 = clkst off (xx) off (xx) x0 ? 0 ? ? fbe (10) x 0 ? 0 ? ercs = 0 scm (00) scm (00) x f icgirclk /7 2 2 the reference frequency has no effect on ic gout in scm, but the reference frequency is still used in making the comparisons that determine the dcos bit. 8/f icgirclk icgdclk/r not switching from fbe to scm ? fei (01) 0 f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? dcos = 0 fbe (10) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? ercs = 0 fee (11) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? dcos = 0 or ercs = 0 fei (01) fei (01) 0 f icgirclk /7 8/f icgirclk icgdclk/r dcos = 1 ? fee (11) x f icgirclk /7 8/f icgirclk icgdclk/r ? ercs = 0 fbe (10) fbe (10) x 0 ? icgerclk/r ercs = 1 ? fee (11) x 0 ? icgerclk/r ? locs = 1 & ercs = 1 fee (11) fee (11) 0 f icgerclk 2/f icgerclk icgdclk/r 3 3 after initial lock; will be icgdclk/2r during initial locking process and while fll is re-locking after the mfd bits are changed. ercs = 1 and dcos = 1 ? 1 f icgerclk 128/f icgerclk icgdclk/r (2) ercs = 1 and dcos = 1 ?
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 115 7.3.9 fixed frequency clock the icg provides a fixed frequency clock output, xclk, for use by on-chip peripherals. this output is equal to the internal bus clock, busclk, in fbe mode. in f ee mode, xclk is equal to icgerclk 2 when the following conditions are met: ?(p n) r 4 where p is determined by range (see table 7-4 ), n and r are determined by mfd and rfd, respectively (see table 7-5 ). ? lock = 1. if the above conditions are not true, then xclk is equal to busclk. when the icg is in either fei or scm mode, xclk is turned off. any peripherals which can use xclk as a clock source must not do so when the icg is in fei or scm mode. 7.3.10 high gain oscillator the oscillator has the option of running in a hi gh gain oscillator (hgo) mode, which improves the oscillator's resistance to emc noise when running in fbe or fee modes. this option is selected by writing a 1 to the hgo bit in the icgc1 regi ster. hgo is used with both the hi gh and low range os cillators but is only valid when refs = 1 in the icgc1 register. wh en hgo = 0, the standard low-power oscillator is selected. if the high gain option is to be swit ched after the initial write to the icgc1 register, then the icg should first be changed to scm or fei mode to stop the exte rnal oscillator. then the hgo bit can be modified and fee or fbe mode can be re-selected in the same write to icgc1. the oscillator will go through the standard start-up delay before the icg switches to the external oscillator 7.4 initialization/application information 7.4.1 introduction this section is intended to give some basic direction on which configuration a user would want to select when initializing the icg. for some applications, the serial communication link may dictate the accuracy of the clock reference. for othe r applications, lowest power consumption may be the chief clock consideration. still others may have lowest cost as the primary goal. th e icg allows great flexibility in choosing which is best for any application.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 116 freescale semiconductor the following sections contain initialization examples for various configurations. note hexadecimal values designated by a pr eceding $, binary values designated by a preceding %, and decimal values have no preceding character. important configuration information is repeated here for reference. table 7-3. icg configuration consideration clock reference source = internal clock reference source = external fll engaged fei 4 mhz < f bus < 20 mhz. medium power (will be less than fee if oscillator range = high) medium clock accuracy (after irg is trimmed) lowest system cost (no external components required) irg is on. dco is on. 1 1 the irg typically consumes 100 a. the fll and dco typically consumes 0.5 to 2.5 ma, depending upon output frequency. for minimum power consumption and minimum jitter, choose n and r to be as small as possible. fee 4 mhz < f bus < 20 mhz medium power (will be less than fei if oscillator range = low) good clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is on. fll bypassed scm this mode is mainly provided for quick and reliable system startup. 3 mhz < f bus < 5 mhz (default). 3 mhz < f bus < 20 mhz (via filter bits). medium power poor accuracy. irg is off. dco is on and open loop. fbe f bus range <= 8 mhz when crystal or resonator is used. lowest power highest clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is off. table 7-4. icgout frequency calculation options clock scheme f icgout 1 1 ensure that f icgdclk , which is equal to f icgout * r, does not exceed f icgdclkmax. pn o t e scm ? self-clocked mode (fll bypassed internal) f icgdclk / r na typical f icgout = 8 mhz out of reset fbe ? fll bypassed external f ext / r na fei ? fll engaged internal (f irg / 7)* 64*n / r 64 typical f irg = 243 khz fee ? fll engaged external f ext * p * n / r range = 0 ; p = 64 range = 1; p = 1
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 117 figure 7-7. icg register set table 7-5. mfd and rfd decode table mfd value multiplication factor (n) rfd division factor (r) 000 4 000 1 001 6 001 2 010 8 010 4 011 10 011 8 100 12 100 16 101 14 101 32 110 16 110 64 111 18 111 128 registerbit 7654321bit 0 icgc1 hgo range refs clks oscsten locd 0 icgc2 lolre mfd locre rfd icgs1 clkst refst lols lock locs ercs icgif icgs2 0 0 0 0 0 0 0 dcos icgfltu 0 0 0 0f l t icgfltl flt icgtrm trim = unimplemented or reserved
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 118 freescale semiconductor 7.4.2 example #1: external crystal = 32 khz, bus frequency = 4.19 mhz in this example, the fll will be used (in fee mode ) to multiply the external 32 khz oscillator up to 8.38 mhz to achieve 4.19 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout, which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be f ll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 64, f ext = 32 khz eqn. 7-1 solving for n / r gives: n / r = 8.38 mhz /(32 khz * 64) = 4 ; we can choose n = 4 and r =1 eqn. 7-2 the values needed in each register to set up the desired operation are: icgc1 = $38 (%00111000) bit 7 hgo 0 configures oscillator for low-power operation bit 6 range 0 configures oscillator for low-fr equency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crys tal or resonator is requested bits 4:3 clks 11 fll engaged, ex ternal reference clock mode bit 2 oscsten 0 oscillator disabled in stop modes bit 1 locd 0 loss-of-clock detection enabled bit 0 0 unimplemented or re served, always reads zero icgc2 = $00 (%00000000) bit 7 lolre 0 generates an interrupt request on loss of lock bits 6:4 mfd 000 sets the mfd multiplication factor to 4 bit 3 locre 0 generates an interrupt request on loss of clock bits 2:0 rfd 000 sets the rfd division factor to 1 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; should read dcos = 1 before performing any time critical tasks icgfltlu/l = $xx only needed in self-clocked mode; flt will be adjusted by loop to give 8.38 mhz dco clock bits 15:12 unused 0000 bits 11:0 flt no need for user initialization icgtrm = $xx bits 7:0 trim only need to write when trimming internal oscillator; not used when external crystal is clock source
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 119 figure 7-8 shows flow charts for three conditions requiring ic g initialization. figure 7-8. icg initialization for fee in example #1 7.4.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz in this example, the fll will be used (in fee mode ) to multiply the external 4 mhz oscillator up to 40-mhz to achieve 20 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). during reset initialization software, the clock scheme will be set to fll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 1, f ext = 4.00 mhz eqn. 7-3 solving for n / r gives: n / r = 40 mhz /(4 mhz * 1) = 10 ; we can choose n = 10 and r = 1 eqn. 7-4 the values needed in each register to set up the desired operation are: icgc1 = $78 (%01111000) bit 7 hgo 0 configures oscillator for low-power operation bit 6 range 1 configures oscillator for high- frequency range; fll pr escale factor is 1 bit 5 refs 1 requests an oscillator bits 4:3 clks 11 fll engaged, ex ternal reference clock mode bit 2 oscsten 0 disables the oscillator in stop modes bit 1 locd 0 loss-of-clock detection enabled bit 0 0 unimplemented or re served, always reads zero recovery from continue recovery from stop3 check lock = 1? no yes fll lock status. initialize icg icg1 = $38 icg2 = $00 recovery from stop3 oscsten = 1 oscsten = 0 continue check lock = 1? no yes fll lock status. continue check lock = 1? no yes fll lock status. note: this will require the oscillator to start and stabilize. actual time is dependent on crystal /resonator and external circuitry. quick recovery from stop minimum current draw in stop reset, stio1, stop2
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 120 freescale semiconductor icgc2 = $30 (%00110000) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 000 sets the rfd division factor to 1 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only. should read dcos befo re performing any time critical tasks icgfltlu/l = $xx not used in this example icgtrm not used in this example figure 7-9. icg initialization and stop recovery for example #2 recovery from continue recovery check lock = 1? no yes fll lock status initialize icg icg1 = $7a icg2 = $30 continue check lock = 1? no yes fll lock status service interrupt source (f bus = 4 mhz) from stop3 reset, stop1, stop2
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 121 7.4.4 example #3: no external cr ystal connection, 5.4 mhz bus frequency in this example, the fll will be used (in fei mode) to multiply the internal 243 khz (approximate) reference clock up to 10.8 mhz to ac hieve 5.4 mhz bus frequency. this system will also use the trim function to fine tune the frequency based on an external reference signal. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be fll engaged, internal (fei). so f icgout = (f irg / 7) * p * n / r ; p = 64, f irg = 243 khz eqn. 7-5 solving for n / r gives: n / r = 10.8 mhz /(243/7 khz * 64) = 4.86 ; we can choose n = 10 and r = 2. eqn. 7-6 a trim procedure will be required to hone the frequency to exac tly 5.4 mhz. an example of the trim procedure is shown in example #4. the values needed in each register to set up the desired operation are: icgc1 = $28 (%00101000) bit 7 hgo 0 configures oscillator for low-power operation bit 6 range 0 configures oscillator for low-fr equency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crystal or resonator requested (bit is really a don?t care) bits 4:3 clks 01 fll engaged, in ternal reference clock mode bit 2 oscsten 0 disables the oscillator in stop modes bit 1 locd 0 loss-of-clock detection enabled bit 0 0 unimplemented or re served, always reads zero icgc2 = $31 (%00110001) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 001 sets the rfd division factor to 2 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; good idea to read this before performing time critical operations icgfltlu/l = $xx not used in this example icgtrm = $xx bit 7:0 trim only need to write when trimmin g internal oscillator ; done in separate operation (see example #4)
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 122 freescale semiconductor figure 7-10. icg initialization and stop recovery for example #3 7.4.5 example #4: internal clock generator trim the internally generated clock sour ce is guaranteed to have a period 25% of the nominal value. in some case this may be sufficient accura cy. for other applications that requi re a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. this section outlines one example of trimming the internal oscillator. many other possi ble trimming procedures are valid and can be used. recovery from continue check lock = 1? no yes fll lock status. initialize icg icg1 = $28 icg2 = $31 recovery continue check lock = 1? no yes fll lock status. note: this will require the interal reference clock to start and stabilize. from stop3 reset, stop1, stop2
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 123 figure 7-11. trim procedure in this particular case, the mcu ha s been attached to a pcb and the entire assembly is undergoing final test with automated test equipment. a separate si gnal or message is provided to the mcu operating under user provided software contro l. the mcu initiates a trim procedure as outlined in figure 7-11 while the tester supplies a precision reference signal. if the intended bus frequency is near the maximum allowed fo r the device, it is re commended to trim using a reduction divisor (r) twice the final value. once th e trim procedure is comp lete, the reduction divisor can be restored. this will prevent accidental overshoot of the maximum clock frequency. 7.5 icg registers and control bits refer to the direct-page register summary in chapter 4, ?memory ? of this data sheet for the absolute address assignments for all icg registers. this secti on refers to registers and control bits only by their names. a freescale-provided equate or header file is used to tr anslate these names into the appropriate absolute addresses. initial conditions: 1) clock supplied from ate has 500 s duty period 2) icg configured for inter nal reference with 4 mhz bus start trim procedure continue case statement count > szzexpected = 500 . measure incoming clock width icgtrm = $80, n = 1 count < expected = 500 count = expected = 500 store icgtrm value in non-volatile memory icgtrm = icgtrm = icgtrm - 128 / (2**n) icgtrm + 128 / (2**n) n = n + 1 (count = # of bus clocks / 4) (decreasing icgtrm increases the frequency) (increasing icgtrm decreases the frequency) no yes is n > 8? (running too slow) (running too fast)
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 124 freescale semiconductor 7.5.1 icg control register 1 (icgc1) 76543210 r hgo range refs clks oscsten locd 0 w r e s e t01000100 = unimplemented or reserved figure 7-12. icg control register 1 (icgc1) table 7-6. icgc1 field descriptions field description 7 hgo high gain oscillator select ? the hgo bit is used to select betw een low-power operation and high-amplitude operation. 0 oscillator configured for low power operation. 1 oscillator configured for high amplitude operation. 6 range frequency range select ? the range bit controls the oscillator, reference divider, and fll loop prescaler multiplication factor (p). it selects one of two refe rence frequency ranges for the icg. the range bit is write-once after a reset. the range bit only has an effect in fll engaged external and fll bypassed external modes. 0 oscillator configured for low frequency range . fll loop prescale factor p is 64. 1 oscillator configured for high frequency ra nge. fll loop prescale factor p is 1. 5 refs external reference select ? the refs bit controls the external reference clock source for icgerclk. the refs bit is write-once after a reset. 0 external clock requested. 1 oscillator using crystal or resonator requested. 4:3 clks clock mode select ? the clks bits control the clock mode. if fl l bypassed external is requested, it will not be selected until ercs = 1. if the icg enters off mode, the clks bits will remain unchanged. writes to the clks bits will not take effect if a previous write is not complete. the clks bits are writable at any time, unless the first write after a reset was clks = 0x, the clks bits cannot be written to 1x until after the next reset (because the extal pin was not reserved). 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference 2 oscsten enable oscillator in off mode ? the oscten bit controls whether or not the oscillator circuit remains enabled when the icg en ters off mode. 0 oscillator disabled when icg is in off mode unless enable is high, clks = 10, and refst = 1. 1 oscillator enabled when icg is in off mode, clks = 1x and refst = 1. 1 locd loss of clock disable 0 loss of clock detection enabled. 1 loss of clock detection disabled.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 125 7.5.2 icg control register 2 (icgc2) 76543210 r lolre mfd locre rfd w r e s e t00000000 figure 7-13. icg control register 2 (icgc2) table 7-7. icgc2 field descriptions field description 7 lolre loss of lock reset enable ? the lolre bit determines what type of request is made by the icg following a loss of lock indication. the lolre bit only has an effect when lols is set. 0 generate an interrupt request on loss of lock. 1 generate a reset request on loss of lock. 6:4 mfd multiplication factor ? the mfd bits control the programmable multip lication factor in the fll loop. the value specified by the mfd bits establishes the multiplication fa ctor (n) applied to the reference frequency. writes to the mfd bits will not take effect if a previous write is not complete. select a low enough value for n such that f icgdclk does not exceed its maximum specified rating. 000 multiplication factor (n) = 4 001 multiplication factor (n) = 6 010 multiplication factor (n) = 8 011 multiplication factor (n) = 10 100 multiplication factor (n) = 12 101 multiplication factor (n) = 14 110 multiplication factor (n) = 16 111 multiplication factor (n) = 18 3 locre loss of clock reset enable ? the locre bit determines how the s ystem handles a loss of clock condition. 0 generate an interrupt request on loss of clock. 1 generate a reset request on loss of clock. 2:0 rfd reduced frequency divider ? the rfd bits control the value of the di vider following the clock select circuitry. the value specified by the rfd bits establishes the division factor (r) applied to the selected output clock source. writes to the rfd bits will not take effect if a previous write is not complete. 000 division factor (r) = 1 001 division factor (r) = 2 010 division factor (r) = 4 011 division factor (r) = 8 100 division factor (r) = 16 101 division factor (r) = 32 110 division factor (r) = 64 111 division factor (r) = 128
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 126 freescale semiconductor 7.5.3 icg status register 1 ( icg s1) 76543210 r clkst refst lols lock locs ercs icg if w 1 reset00000000 = unimplemented or reserved figure 7-14. icg status register 1 (icgs1) table 7-8. icgs1 field descriptions field description 7:6 clkst clock mode status ? the clkst bits indicate the current clock mode. the clkst bits don?t update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference 5 refst reference clock status ? the refst bit indicates which clock re ference is currently selected by the reference select circuit. 0 external clock selected. 1 crystal/resonator selected. 4 lols fll loss of lock status ? the lols bit is an indication of fll-lock status. if lols is set, it remains set until cleared by clearing the icgif flag or an mcu reset. 0 fll has not unexpectedly lost lock since lols was last cleared. 1 fll has unexpectedly lost lock since lols was last cleared, lolre determines action taken. 3 lock fll lock status ? the lock bit indicates whether the fll has ac quired lock. the lock bit is cleared in off, self-clocked, and fll bypassed modes. 0 fll is currently unlocked. 1 fll is currently locked. 2 locs loss of clock status ? the locs bit is an indication of icg loss-of-c lock status. if locs is set, it remains set until cleared by clearing the icgif flag or an mcu reset. 0 icg has not lost clock since locs was last cleared. 1 icg has lost clock since locs was last cleared, locre determines action taken. 1 ercs external reference clock status ? the ercs bit is an indication of whether or not the external reference clock (icgerclk) meets the minimum frequency requirement. 0 external reference clock is not stable, frequency requirement is not met. 1 external reference clock is stable, frequency requirement is met. 0 icg if icg interrupt flag ? the icgif read/write flag is set when an icg interrupt request is pending. it is cleared by a reset or by reading the icg status register when icgi f is set and then writing a 1 to icgif. if another icg interrupt occurs before the clearing sequence is complete, the sequence is reset so icgif would remain set after the clear sequence was completed for the earlier interrupt. writing a 0 to icgif has no effect. 0 no icg interrupt request is pending. 1 an icg interrupt request is pending.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 127 7.5.4 icg status register 2 (icgs2) 7.5.5 icg filter registers (icgfltu, icgfltl) the filter registers show the filter value (flt). 76543210 r0000000d c o s w r e s e t00000000 = unimplemented or reserved figure 7-15. icg status register 2 (icgs2) table 7-9. icgs2 field descriptions field description 0 dcos dco clock stable ? the dcos bit is set when the dco clock (icg2dclk) is stable, meaning the count error has not changed by more than n unlock for two consecutive samples and the dco clock is not static. this bit is used when exiting off state if clks = x1 to determine when to switch to the requested clock mode. it is also used in self-clocked mode to determine when to start monitori ng the dco clock. this bit is cleared upon entering the off state. 0 dco clock is unstable. 1 dco clock is stable. 76543210 r 0000 flt w r e s e t00000000 = unimplemented or reserved figure 7-16. icg upper filter register (icgfltu) table 7-10. icgfltu field descriptions field description 3:0 flt filter value ? the flt bits indicate the current filter value, which controls the dco frequency. the flt bits are read only except when the clks bits are programmed to self-clocked mode (clks = 00). in self-clocked mode, any write to icgfltu updates the current 12-bit filter value. writes to the ic gfltu register will not affect flt if a previous latch sequence is not complete.
internal clock generator (s08icgv2) mc9s08gb60a data sheet, rev. 2 128 freescale semiconductor 7.5.6 icg trim register (icgtrm) 76543210 r flt w r e s e t11000000 = unimplemented or reserved figure 7-17. icg upper filter register (icgfltl) table 7-11. icgfltl field descriptions field description 7:0 flt filter value ? the flt bits indicate the current filter value, which controls the dco frequency. the flt bits are read only except when the clks bits are programmed to self-clocked mode (clks = 00). in self-clocked mode, any write to icgfltu updates the current 12-bit filter value. writes to the ic gfltu register will not affect flt if a previous latch sequence is not complete. 76543210 r trim w por:10000000 reset:uuuuuuuu = unimplemented or reserved u = unaffected by mcu reset figure 7-18. icg trim register (icgtrm) table 7-12. icgtrm field descriptions field description 7:0 trim icg trim setting ? the trim bits control the internal reference generator frequency. they allow a 25% adjustment of the nominal (por) period. the bit?s effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). increasing the binary value in trim will increase the period and decreasing the value will decrease the period.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 129 chapter 8 central processor unit (s08cpuv2) 8.1 introduction this section provides summary information about the re gisters, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor documen t order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code -compatible with the m68hc08 cpu. several instructions and enhanced addressi ng modes were added to improve c compiler efficiency and to support a new background debug system which replaces the m onitor mode of earlier m68hc08 microcontrollers (mcu). 8.1.1 features features of the hcs08 cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? all registers and memory are mappe d to a single 64-kbyte address space ? 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: ? inherent ? operands in internal registers ? relative ? 8-bit signed offs et to branch destination ? immediate ? operand in next object code byte(s) ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kbyte address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 130 freescale semiconductor 8.2 programmer?s model and cpu registers figure 8-1 shows the five cpu registers. cpu regi sters are not part of the memory map. figure 8-1. cpu registers 8.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit regist er. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu re sults are often stored into the a accumulator after arithmetic and logical ope rations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data co mes from, or the contents of a can be stored to memory using various addressing m odes to specify the address where data from a will be stored. reset has no effect on the c ontents of the a accumulator. 8.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit regist ers (h and x), which often work together as a 16-bit address pointer where h holds the upp er byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc 05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8- bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, co mplemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or tr ansferred to a where arithm etic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is fo rced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 131 8.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available locati on on the automatic last-in-first-out (lifo) stack. the stack may be lo cated anywhere in the 64-kbyte a ddress space that has ram and can be any size up to the amount of available ram. the stac k is used to automaticall y save the return address for subroutine calls, the return address and cpu regi sters during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate valu e to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc 05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ra m (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was includ ed for compatibility with the m68hc05 family and is seldom used in new hcs08 progr ams because it only affects the low- order half of the stack pointer. 8.2.4 program counter (pc) the program counter is a 16-bit register that contai ns the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an in struction or operand is fetched. ju mp, branch, interrupt, and return operations load the program counter with an address ot her than that of the next sequential location. this is called a change-of-flow. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the first in struction that will be execu ted after exiting the reset state. 8.2.5 condition code register (ccr) the 8-bit condition code register contai ns the interrupt mask (i) and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set pe rmanently to 1. the following paragraphs describe the functions of the condition code bits in general term s. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1.
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 132 freescale semiconductor figure 8-2. condition code register table 8-1. ccr register field descriptions field description 7 v two?s complement overflow flag ? the cpu sets the overflow flag when a two?s complement overflow occurs. the signed branch instructions bgt, bg e, ble, and blt use the overflow flag. 0 no overflow 1overflow 4 h half-carry flag ? the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operati on. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction us es the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ? when the interrupt mask is set, all maska ble cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers ar e saved on the stack, but before the firs t instruction of the interrupt service routine is executed. interrupts are not recognized at the inst ruction boundary after any instruction that clears i (cli or tap). this ensures that the next instru ction after a cli or tap will always be execut ed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ? the cpu sets the negative flag when an arithmetic operation, logi c operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most significant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ? the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1zero result 0 c carry/borrow flag ? the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation require s a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow 70 ccr c v11hinz
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 133 8.3 addressing modes addressing modes define the way th e cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/out put (i/o) ports share a single 64-kbyt e linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access va riables in ram can also be used to acce ss i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, m ove instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and db nz use one addressing mode to specify the location of an operand for a test and then use relative addres sing mode to specify the branch destination address when the tested condition is true . for brclr, brset, cbeq, and dbnz , the addressing mode listed in the instruction set tables is the addressing mode need ed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 8.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 8.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination locatio n for branch instructions. a signed 8-bit offset value is located in the memory location immediate ly following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 8.3.3 immediate addressing mode (imm) in immediate addressing mode, the op erand needed to complete the inst ruction is included in the object code immediately followi ng the instruction opcode in memory. in the case of a 16-bi t immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memo ry location after that. 8.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?0x00ff). during execution a 16-bit address is formed by concatenati ng an implied 0x00 for the high-order half of the address and th e direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory efficien t than specifying a complete 16-bit address for the operand.
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 134 freescale semiconductor 8.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 indexed addressing mode indexed addressing mode has seven variations including five that use the 16-bit h:x index register pair and two that use the stack po inter as the base reference. 8.3.6.1 indexed, no offset (ix) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 8.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 8.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. 8.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 8.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit va lue in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 135 8.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 special operations the cpu performs a few special opera tions that are similar to instruct ions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop a nd wait directly affect other mcu circuitry. this section provides additional informat ion about these operations. 8.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determin es the source, refer to the resets, interrupts, and system configuration chapter. the reset event is considered conc luded when the sequence to determin e whether the reset came from an internal source is done and when the reset pin is no longer asse rted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0x fffe and 0xffff and to fill the instruction queue in preparation for execution of the first program instruction. 8.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority in terrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program info rmation starting at the address i ndicated by the interrupt vector to fill the instruction queue in preparation for ex ecution of the first instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routin e. although it is possible to clear th e i bit with an instruction in the
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 136 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are di fficult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the hi gh-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt se quence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certa in that the interr upt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a ha rdware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 8.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumpt ion while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event oc curs, the cpu clocks will resume and the interrupt or reset even t will be processed normally. if a serial background comma nd is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu cloc ks will resume and th e cpu will enter activ e background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu ev en if it is in wait mode. 8.4.4 stop mode operation usually, all system clocks, includi ng the crystal oscillator (when used ), are halted during stop mode to minimize power consumption. in such systems, external circui try is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be configured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodi c signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial back ground command is issued to the mc u through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial backgr ound commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode de pends on the particular hcs08 and whether the osc illator was stopped in stop mode. refer to the modes of operation chapter for more details.
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 137 8.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compar ed to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to st op processing user instructions and enter the active background mode. the only way to re sume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program re aches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program.
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 138 freescale semiconductor 8.5 hcs08 instruction set summary instruction set summary nomenclature the nomenclature listed here is used in the instruction descriptions in table 8-2 . operators ( ) = contents of register or memory location shown inside parentheses = is loaded with (read: ?gets?) &= boolean and |= boolean or = boolean exclusive-or = multiply = divide := concatenate += add ?= negate (two?s complement) cpu registers a= accumulator ccr = condition code register h= index register, higher order (most significant) 8 bits x= index register, lower orde r (least significant) 8 bits pc = program counter pch = program counter, higher orde r (most significant) 8 bits pcl = program counter, lower order (least significant) 8 bits sp = stack pointer memory and addressing m = a memory location or absolute data, depending on addressing mode m:m + 0x0001= a 16-bit value in two consecutive memo ry locations. the higher-order (most significant) 8 bits are located at the address of m, and th e lower-order (least significant) 8 bits are located at the next higher sequential address. condition code register (ccr) bits v= two?s complement overflow indicator, bit 7 h= half carry, bit 4 i= interrupt mask, bit 3 n= negative indicator, bit 2 z= zero indicator, bit 1 c= carry/borrow, bit 0 ( carry out of bit 7) ccr activity notation ?= bit not affected
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 139 0= bit forced to 0 1= bit forced to 1 t = bit set or cleared according to results of operation u= undefined after the operation machine coding notation dd = low-order 8 bits of a di rect address 0x0000?0x00ff (high byte assumed to be 0x00) ee = upper 8 bits of 16-bit offset ff = lower 8 bits of 16-bit offset or 8-bit offset ii = one byte of immediate data jj = high-order byte of a 16-bi t immediate data value kk = low-order byte of a 16-b it immediate data value hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr = relative offset source form everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the assembly source file exactly as s hown. the initial 3- to 5-le tter mnemonic is always a literal expression. all comm as, pound signs (#), parentheses, and pl us signs (+) are literal characters. n ? any label or expression that evaluates to a single integer in the range 0?7 opr8i ? any label or expression that evalua tes to an 8-bit immediate value opr16i ? any label or expression that eval uates to a 16-bit immediate value opr8a ? any label or expression that ev aluates to an 8-bit value. th e instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64-kbyte address space (0x00xx). opr16a ? any label or expression that evaluates to a 16-bit value. the instruction treats this value as an address in the 64-kbyte address space. oprx8 ? any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 ? any label or expression that evaluates to a 16-bit value. because the hcs08 has a 16-bit address bus, this can be eith er a signed or an unsigned value. rel ? any label or expression that refers to an a ddress that is within ?128 to +127 locations from the next address after the last byte of object code for the current instruction. the assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. address modes inh = inherent (no operands) imm = 8-bit or 16-bit immediate dir = 8-bit direct ext = 16-bit extended
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 140 freescale semiconductor ix = 16-bit indexed no offset ix+ = 16-bit indexed no offset, post increment (cbe q and mov only) ix1 = 16-bit indexed with 8- bit offset from h:x ix1+ = 16-bit indexed with 8-bi t offset, post increment (cbeq only) ix2 = 16-bit indexed with 16- bit offset from h:x rel = 8-bit relative offset sp1 = stack pointer with 8-bit offset sp2 = stack pointer with 16-bit offset table 8-2. hcs08 instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc adc # opr8i adc opr8a adc opr16a adc oprx16,x adc oprx8 ,x adc ,x adc oprx16,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) || ? ||| imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9ed9 9ee9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 add # opr8i add opr8a add opr16a add oprx16,x add oprx8 ,x add ,x add oprx16,sp add oprx8 ,sp add without carry a (a) + (m) || ? ||| imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9edb 9eeb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ais # opr8i add imme diate value (signed) to stack pointer sp (sp) + (m) m is sign extended to a 16-bit value ??????imm a7ii 2 aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) m is sign extended to a 16-bit value ??????imm afii 2 and # opr8i and opr8a and opr16a and oprx16,x and oprx8 ,x and ,x and oprx16,sp and oprx8 ,sp logical and a (a) & (m) 0 ? ? || ? imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9ed4 9ee4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) | ?? ||| dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,s p arithmetic shift right | ?? ||| dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 5 1 1 5 4 6 bcc rel branch if carry bit clear branch if (c) = 0 ? ? ? ? ? ? rel 24 rr 3 c b0 b7 0 b0 b7 c
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 141 bclr n,opr8a clear bit n in memory mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) branch if (c) = 1 ?????? rel 25 rr 3 beq rel branch if equal branch if (z) = 1 ?????? rel 27 rr 3 bge rel branch if greater than or equal to (signed operands) branch if (n v ) = 0 ?????? rel 90 rr 3 bgnd enter active background if enbdm = 1 waits for and processes bdm commands until go, trace1, or taggo ?????? inh 82 5+ bgt rel branch if greater than (signed operands) branch if (z) | (n v ) = 0 ?????? rel 92 rr 3 bhcc rel branch if half carry bit clear branch if (h) = 0 ?????? rel 28 rr 3 bhcs rel branch if half carry bit set branch if (h) = 1 ?????? rel 29 rr 3 bhi rel branch if higher branch if (c) | (z) = 0 ?????? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) branch if (c) = 0 ?????? rel 24 rr 3 bih rel branch if irq pin high branch if irq pin = 1 ?????? rel 2f rr 3 bil rel branch if irq pin low branch if irq pin = 0 ?????? rel 2e rr 3 bit # opr8i bit opr8a bit opr16a bit oprx16,x bit oprx8 ,x bit ,x bit oprx16,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) 0?? || ? imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9ed5 9ee5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ble rel branch if less than or equal to (signed operands) branch if (z) | (n v ) = 1 ?????? rel 93 rr 3 blo rel branch if lower (same as bcs) branch if (c) = 1 ?????? rel 25 rr 3 bls rel branch if lower or same branch if (c) | (z) = 1 ?????? rel 23 rr 3 blt rel branch if less than (signed operands) branch if (n v ) = 1 ?????? rel 91 rr 3 bmc rel branch if interrupt mask clear branch if (i) = 0 ?????? rel 2c rr 3 bmi rel branch if minus branch if (n) = 1 ?????? rel 2b rr 3 bms rel branch if interrupt mask set branch if (i) = 1 ?????? rel 2d rr 3 bne rel branch if not equal branch if (z) = 0 ?????? rel 26 rr 3 bpl rel branch if plus branch if (n) = 0 ?????? rel 2a rr 3 bra rel branch always no test ?????? rel 20 rr 3 table 8-2. hcs08 instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 142 freescale semiconductor brclr n,opr8a,rel branch if bit n in memory clear branch if (mn) = 0 ????? | dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never uses 3 bus cycles ?????? rel 21 rr 3 brset n,opr8a ,rel branch if bit n in memory set branch if (mn) = 1 ????? | dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n, opr8a set bit n in memory mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 0x0002 push (pcl); sp (sp) ? 0x0001 push (pch); sp (sp) ? 0x0001 pc (pc) + rel ?????? rel ad rr 5 cbeq opr8a ,rel cbeqa # opr8i ,rel cbeqx # opr8i ,rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and branch if equal branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 clc clear carry bit c 0 ?????0 inh 98 1 cli clear interrupt mask bit i 0 ??0??? inh 9a 1 clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m 0x00 a 0x00 x 0x00 h 0x00 m 0x00 m 0x00 m 0x00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 5 1 1 1 5 4 6 cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory (a) ? (m) (ccr updated but operands not changed) | ?? ||| imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9ed1 9ee1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement (one?s complement) m (m )= 0xff ? (m) a (a ) = 0xff ? (a) x (x ) = 0xff ? (x) m (m ) = 0xff ? (m) m (m ) = 0xff ? (m) m (m ) = 0xff ? (m) 0?? || 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 5 1 1 5 4 6 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ? (m:m + 0x0001) (ccr updated but operands not changed) | ?? ||| ext imm dir sp1 3e 65 75 9ef3 hh ll jj kk dd ff 6 3 5 6 table 8-2. hcs08 instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 143 cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory (x) ? (m) (ccr updated but operands not changed) | ?? ||| imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9ed3 9ee3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 daa decimal adjust accumulator after add or adc of bcd values (a) 10 u?? ||| inh 72 1 dbnz opr8a,rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement and branch if not zero decrement a, x, or m branch if (result) 0 dbnzx affects x not h ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ? 0x01 a (a) ? 0x01 x (x) ? 0x01 m (m) ? 0x01 m (m) ? 0x01 m (m) ? 0x01 | ?? || ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 5 1 1 5 4 6 div divide a (h:a) (x) h remainder ???? || inh 52 6 eor # opr8i eor opr8a eor opr16a eor oprx16,x eor oprx8 ,x eor ,x eor oprx16,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) 0?? || ? imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9ed8 9ee8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + 0x01 a (a) + 0x01 x (x) + 0x01 m (m) + 0x01 m (m) + 0x01 m (m) + 0x01 | ?? || ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 5 1 1 5 4 6 jmp opr8a jmp opr16a jmp oprx16,x jmp oprx8 ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 jsr opr8a jsr opr16a jsr oprx16,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 0x0001 push (pch); sp (sp) ? 0x0001 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 lda # opr8i lda opr8a lda opr16a lda oprx16 ,x lda oprx8 ,x lda ,x lda oprx16 ,sp lda oprx8 ,sp load accumulator from memory a (m) 0?? || ? imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9ed6 9ee6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16,x ldhx oprx8 ,x ldhx oprx8 ,sp load index register (h:x) from memory h:x ( m:m + 0x0001 ) 0?? || ? imm dir ext ix ix2 ix1 sp1 45 55 32 9eae 9ebe 9ece 9efe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 table 8-2. hcs08 instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 144 freescale semiconductor ldx # opr8i ldx opr8a ldx opr16a ldx oprx16 ,x ldx oprx8 ,x ldx ,x ldx oprx16 ,sp ldx oprx8 ,sp load x (index register low) from memory x (m) 0?? || ? imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9ede 9eee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 lsl opr8a lsla lslx lsl oprx8,x lsl ,x lsl oprx8,sp logical shift left (same as asl) | ?? ||| dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right | ??0 || dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 5 1 1 5 4 6 mov opr8a ,opr8a mov opr8a ,x+ mov #opr8i ,opr8a mov ,x+, opr8a move (m) destination (m) source h:x (h:x) + 0x0001 in ix+/dir and dir/ix+ modes 0?? || ? dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 mul unsigned multiply x:a (x) (a) ?0???0 inh 42 5 neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate (two?s complement) m ? (m) = 0x00 ? (m) a ? (a) = 0x00 ? (a) x ? (x) = 0x00 ? (x) m ? (m) = 0x00 ? (m) m ? (m) = 0x00 ? (m) m ? (m) = 0x00 ? (m) | ?? ||| dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 5 1 1 5 4 6 nop no operation uses 1 bus cycle ?????? inh 9d 1 nsa nibble swap accumulator a (a[3:0]:a[7:4]) ?????? inh 62 1 ora # opr8i ora opr8a ora opr16a ora oprx16,x ora oprx8 ,x ora ,x ora oprx16,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) 0?? || ? imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9eda 9eea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 psha push accumulator onto stack push (a); sp (sp ) ? 0x0001 ?????? inh 87 2 pshh push h (index register high) onto stack push (h) ; sp (sp ) ? 0x0001 ?????? inh 8b 2 pshx push x (index register low) onto stack push (x) ; sp (sp ) ? 0x0001 ?????? inh 89 2 pula pull accumulator from stack sp (sp + 0x0001); pull ( a ) ?????? inh 86 3 pulh pull h (index register high) from stack sp (sp + 0x0001); pull ( h) ?????? inh 8a 3 pulx pull x (index register low) from stack sp (sp + 0x0001); pull ( x ) ?????? inh 88 3 rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry | ?? ||| dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 5 1 1 5 4 6 table 8-2. hcs08 instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc c b0 b7 0 b0 b7 c 0 c b0 b7
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 145 ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry | ?? ||| dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 5 1 1 5 4 6 rsp reset stack pointer sp 0xff (high byte not affected) ?????? inh 9c 1 rti return from interrupt sp (sp) + 0x0001; pull (ccr) sp (sp) + 0x0001; pull (a) sp (sp) + 0x0001; pull (x) sp (sp) + 0x0001; pull (pch) sp (sp) + 0x0001; pull (pcl) |||||| inh 80 9 rts return from subroutine sp sp + 0x0001 ; pull ( pch) sp sp + 0x0001; pull (pcl) ?????? inh 81 6 sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ? (m) ? (c) | ?? ||| imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9ed2 9ee2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 sec set carry bit c 1 ?????1 inh 99 1 sei set interrupt mask bit i 1 ??1??? inh 9b 1 sta opr8a sta opr16a sta oprx16 ,x sta oprx8 ,x sta ,x sta oprx16 ,sp sta oprx8 ,sp store accumulator in memory m (a) 0?? || ? dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9ed7 9ee7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + 0x0001) (h:x) 0?? || ? dir ext sp1 35 96 9eff dd hh ll ff 4 5 5 stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing ??0??? inh 8e 2+ stx opr8a stx opr16a stx oprx16 ,x stx oprx8 ,x stx ,x stx oprx16 ,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) 0?? || ? dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9edf 9eef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) ? (m) | ?? ||| imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9ed0 9ee0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 swi software interrupt pc (pc) + 0x0001 push (pcl); sp (sp) ? 0x0001 push (pch); sp (sp) ? 0x0001 push (x); sp (sp) ? 0x0001 push (a); sp (sp) ? 0x0001 push (ccr); sp (sp) ? 0x0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte ??1??? inh 83 11 table 8-2. hcs08 instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc b0 b7 c
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 146 freescale semiconductor tap transfer accumulator to ccr ccr (a) |||||| inh 84 1 tax transfer accumulator to x (index register low) x (a) ?????? inh 97 1 tpa transfer ccr to accumulator a (ccr) ?????? inh 85 1 tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ? 0x00 (a) ? 0x00 (x) ? 0x00 (m) ? 0x00 (m) ? 0x00 (m) ? 0x00 0?? || ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 4 1 1 4 3 5 tsx transfer sp to index reg. h:x (sp) + 0x0001 ?????? inh 95 2 txa transfer x (index reg. low) to accumulator a (x) ?????? inh 9f 1 txs transfer index reg. to sp sp (h:x) ? 0x0001 ?????? inh 94 2 wait enable interrupts; wait for interrupt i bit 0; halt cpu ??0??? inh 8f 2+ 1 bus clock frequency is one-half of the cpu clock frequency. table 8-2. hcs08 instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 147 table 8-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modi fy-write control register/memory 00 5 brset0 3dir 10 5 bset0 2dir 20 3 bra 2rel 30 5 neg 2dir 40 1 nega 1inh 50 1 negx 1inh 60 5 neg 2ix1 70 4 neg 1ix 80 9 rti 1inh 90 3 bge 2rel a0 2 sub 2imm b0 3 sub 2dir c0 4 sub 3 ext d0 4 sub 3ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3dir 11 5 bclr0 2dir 21 3 brn 2rel 31 5 cbeq 3dir 41 4 cbeqa 3imm 51 4 cbeqx 3imm 61 5 cbeq 3ix1+ 71 5 cbeq 2ix+ 81 6 rts 1inh 91 3 blt 2rel a1 2 cmp 2imm b1 3 cmp 2dir c1 4 cmp 3 ext d1 4 cmp 3ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3dir 12 5 bset1 2dir 22 3 bhi 2rel 32 5 ldhx 3ext 42 5 mul 1inh 52 6 div 1inh 62 1 nsa 1inh 72 1 daa 1inh 82 5+ bgnd 1inh 92 3 bgt 2rel a2 2 sbc 2imm b2 3 sbc 2dir c2 4 sbc 3 ext d2 4 sbc 3ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3dir 13 5 bclr1 2dir 23 3 bls 2rel 33 5 com 2dir 43 1 coma 1inh 53 1 comx 1inh 63 5 com 2ix1 73 4 com 1ix 83 11 swi 1inh 93 3 ble 2rel a3 2 cpx 2imm b3 3 cpx 2dir c3 4 cpx 3 ext d3 4 cpx 3ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3dir 14 5 bset2 2dir 24 3 bcc 2rel 34 5 lsr 2dir 44 1 lsra 1inh 54 1 lsrx 1inh 64 5 lsr 2ix1 74 4 lsr 1ix 84 1 ta p 1inh 94 2 txs 1inh a4 2 and 2imm b4 3 and 2dir c4 4 and 3 ext d4 4 and 3ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3dir 15 5 bclr2 2dir 25 3 bcs 2rel 35 4 sthx 2dir 45 3 ldhx 3imm 55 4 ldhx 2dir 65 3 cphx 3imm 75 5 cphx 2dir 85 1 tpa 1inh 95 2 tsx 1inh a5 2 bit 2imm b5 3 bit 2dir c5 4 bit 3 ext d5 4 bit 3ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3dir 16 5 bset3 2dir 26 3 bne 2rel 36 5 ror 2dir 46 1 rora 1inh 56 1 rorx 1inh 66 5 ror 2ix1 76 4 ror 1ix 86 3 pula 1inh 96 5 sthx 3ext a6 2 lda 2imm b6 3 lda 2dir c6 4 lda 3 ext d6 4 lda 3ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3dir 17 5 bclr3 2dir 27 3 beq 2rel 37 5 asr 2dir 47 1 asra 1inh 57 1 asrx 1inh 67 5 asr 2ix1 77 4 asr 1ix 87 2 psha 1inh 97 1 ta x 1inh a7 2 ais 2imm b7 3 sta 2dir c7 4 sta 3 ext d7 4 sta 3ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3dir 18 5 bset4 2dir 28 3 bhcc 2rel 38 5 lsl 2dir 48 1 lsla 1inh 58 1 lslx 1inh 68 5 lsl 2ix1 78 4 lsl 1ix 88 3 pulx 1inh 98 1 clc 1inh a8 2 eor 2imm b8 3 eor 2dir c8 4 eor 3 ext d8 4 eor 3ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3dir 19 5 bclr4 2dir 29 3 bhcs 2rel 39 5 rol 2dir 49 1 rola 1inh 59 1 rolx 1inh 69 5 rol 2ix1 79 4 rol 1ix 89 2 pshx 1inh 99 1 sec 1inh a9 2 adc 2imm b9 3 adc 2dir c9 4 adc 3 ext d9 4 adc 3ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3dir 1a 5 bset5 2dir 2a 3 bpl 2rel 3a 5 dec 2dir 4a 1 deca 1inh 5a 1 decx 1inh 6a 5 dec 2ix1 7a 4 dec 1ix 8a 3 pulh 1inh 9a 1 cli 1inh aa 2 ora 2imm ba 3 ora 2dir ca 4 ora 3 ext da 4 ora 3ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3dir 1b 5 bclr5 2dir 2b 3 bmi 2rel 3b 7 dbnz 3dir 4b 4 dbnza 2inh 5b 4 dbnzx 2inh 6b 7 dbnz 3ix1 7b 6 dbnz 2ix 8b 2 pshh 1inh 9b 1 sei 1inh ab 2 add 2imm bb 3 add 2dir cb 4 add 3 ext db 4 add 3ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3dir 1c 5 bset6 2dir 2c 3 bmc 2rel 3c 5 inc 2dir 4c 1 inca 1inh 5c 1 incx 1inh 6c 5 inc 2ix1 7c 4 inc 1ix 8c 1 clrh 1inh 9c 1 rsp 1inh bc 3 jmp 2dir cc 4 jmp 3 ext dc 4 jmp 3ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3dir 1d 5 bclr6 2dir 2d 3 bms 2rel 3d 4 tst 2dir 4d 1 tsta 1inh 5d 1 tstx 1inh 6d 4 tst 2ix1 7d 3 tst 1ix 9d 1 nop 1inh ad 5 bsr 2rel bd 5 jsr 2dir cd 6 jsr 3 ext dd 6 jsr 3ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3dir 1e 5 bset7 2dir 2e 3 bil 2rel 3e 6 cphx 3ext 4e 5 mov 3dd 5e 5 mov 2dix+ 6e 4 mov 3imd 7e 5 mov 2ix+d 8e 2+ stop 1inh 9e page 2 ae 2 ldx 2imm be 3 ldx 2dir ce 4 ldx 3 ext de 4 ldx 3ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3dir 1f 5 bclr7 2dir 2f 3 bih 2rel 3f 5 clr 2dir 4f 1 clra 1inh 5f 1 clrx 1inh 6f 5 clr 2ix1 7f 4 clr 1ix 8f 2+ wait 1inh 9f 1 txa 1inh af 2 aix 2imm bf 3 stx 2dir cf 4 stx 3 ext df 4 stx 3ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 8 central processor unit (s08cpuv2) mc9s08gb60a data sheet, rev. 2 148 freescale semiconductor bit-manipulation branch read-modi fy-write control register/memory 9e60 6 neg 3sp1 9ed0 5 sub 4sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4sp1 9ed1 5 cmp 4sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4sp2 9ee2 4 sbc 3sp1 9e63 6 com 3sp1 9ed3 5 cpx 4sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3sp1 9e64 6 lsr 3sp1 9ed4 5 and 4sp2 9ee4 4 and 3sp1 9ed5 5 bit 4sp2 9ee5 4 bit 3sp1 9e66 6 ror 3sp1 9ed6 5 lda 4sp2 9ee6 4 lda 3sp1 9e67 6 asr 3sp1 9ed7 5 sta 4sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3sp1 9ed8 5 eor 4sp2 9ee8 4 eor 3sp1 9e69 6 rol 3sp1 9ed9 5 adc 4sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3sp1 9eda 5 ora 4sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4sp1 9edb 5 add 4sp2 9eeb 4 add 3sp1 9e6c 6 inc 3sp1 9e6d 5 tst 3sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4ix2 9ece 5 ldhx 3ix1 9ede 5 ldx 4sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3sp1 9e6f 6 clr 3sp1 9edf 5 stx 4sp2 9eef 4 stx 3sp1 9eff 5 sthx 3sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3sp1 hcs08 cycles instruction mnemonic addressing mode table 8-3. opcode map (sheet 2 of 2)
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 149 chapter 9 keyboard interrupt (s08kbiv1) 9.1 introduction the mc9s08gbxxa/gtxxa has one kbi module with eight keyboard interrupt inputs that share port a pins. see chapter 2, ?pins and connections ? for more information about the logic and hardware aspects of these pins. 9.1.1 port a and keyboard interrupt pins figure 9-1. port a pin names the following paragraphs discuss cont rolling the keyboard interrupt pins. port a is an 8-bit port which is shared among the kbi keyboard interrupt inputs and general-purpose i/o. the eight kbipen control bits in th e kbipe register allow se lection of any combinat ion of port a pins to be assigned as kbi inputs. any pins which are enabled as kbi inputs will be forced to act as inputs and the remaining port a pins are available as general- purpose i/o pins controlled by the port a data (ptad), data direction (ptadd), and pul lup enable (ptape) registers. kbi inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. bits 3 through 0 of port a are falling-edge/l ow-level sensitive while bits 7 through 4 can be configured for rising-edge/high-level or for falling-edge/low-level sensitivity. the eight ptapen control bits in th e ptape register allow you to select whether an internal pullup device is enabled on each port a pin that is configured as an input. when any of bits 7 through 4 of port a are enabled as kbi inputs and ar e configured to detect ri sing edges/high leve ls, the pullup enable bits enable pulldown rather than pullup devices. an enabled keyboard interrupt can be used to wake the mcu from wait or standby (stop3). 9.2 features the keyboard interrupt (kbi) module features include: ? keyboard interrupts selectable on eight port pins: ? four falling-edge/low-level sensitive ? four falling-edge/low-level or rising-edge/high-level sensitive ? choice of edge-only or edge-and-level sensitivity ? common interrupt flag and interrupt enable control ? capable of waking up the mcu from stop3 or wait mode mcu pin: pta7/ kbi1p7 pta6/ kbi1p6 pta5/ kbi1p5 pta4/ kbi1p4 pta3/ kbi1p3 pta2/ kbi1p2 pta1/ kbi1p1 pta0/ kbi1p0
chapter 9 keyboard interrupt (s08kbiv1) mc9s08gb60a data sheet, rev. 2 150 freescale semiconductor figure 9-2. block diagram highlighting kbi module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
keyboard interrupt (s08kbiv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 151 9.2.1 kbi block diagram figure 9-3 shows the block diagram for a kbi module. figure 9-3. kbi block diagram 9.3 register definition this section provides information about all registers and control bits associated with the kbi module. refer to the direct-page register summ ary in the memory chapter of this data sheet for the absolute address assignments for all kbi registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. keyboard interrupt dq ck clr v dd kbimod kbie keyboard interrupt ff request kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 kbipe3 kbipe4 0 1 s kbedg4 kbi1p0 kbi1p3 kbi1p4 kbi1pn
keyboard interrupt (s08kbiv1) mc9s08gb60a data sheet, rev. 2 152 freescale semiconductor 9.3.1 kbi status and control register (kbi1sc) 76543210 r kbedg7 kbedg6 kbedg5 kbedg4 kbf 0 kbie kbimod w kback reset00000000 = unimplemented or reserved figure 9-4. kbi status and control register (kbi1sc) table 9-1. kbi1sc register field descriptions field description 7:4 kbedg[7:4] keyboard edge select for kbi port bits ? each of these read/write bits sele cts the polarity of the edges and/or levels that are recognized as trigger events on the corresp onding kbi port pin when it is configured as a keyboard interrupt input (kbipen = 1). also see the kbimod control bit, which determines whether the pin is sensitive to edges-only or edges and levels. 0 falling edges/low levels 1 rising edges/high levels 3 kbf keyboard interrupt flag ? this read-only status flag is set whenever the selected edge event has been detected on any of the enabled kbi port pins. this flag is cleared by writing a 1 to the kback control bit. the flag will remain set if kbimod = 1 to select edge-and-level operation and any enabled kbi port pin remains at the asserted level. kbf can be used as a software pollable flag (kbie = 0) or it can generate a hardware interrupt request to the cpu (kbie = 1). 0 no kbi interrupt pending 1 kbi interrupt pending 2 kback keyboard interrupt acknowledge ? this write-only bit (reads always return 0) is used to clear the kbf status flag by writing a 1 to kback. when kbimod = 1 to sele ct edge-and-level operation and any enabled kbi port pin remains at the asserted level, kbf is being continuous ly set so writing 1 to kback does not clear the kbf flag. 1 kbie keyboard interrupt enable ? this read/write control bit determines whether hardware interrupts are generated when the kbf status flag equals 1. when kbie = 0, no hardware interrupt s are generated, but kbf can still be used for software polling. 0 kbf does not generate hardware interrupts (use polling) 1 kbi hardware interrupt requested when kbf = 1 kbimod keyboard detection mode ? this read/write control bit selects either edge-only detection or edge-and-level detection. kbi port bits 3 through 0 can detect falling edges-only or falling edges and low levels. kbi port bits 7 through 4 can be configured to detect either: ? rising edges-only or rising edges and high levels (kbedgn = 1) ? falling edges-only or falling edges and low levels (kbedgn = 0) 0 edge-only detection 1 edge-and-level detection
keyboard interrupt (s08kbiv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 153 9.3.2 kbi pin enable register (kbi1pe) 9.4 functional description 9.4.1 pin enables the kbipen control bits in the kbi1 pe register allow a user to enab le (kbipen = 1) any combination of kbi-related port pins to be conn ected to the kbi module. pins co rresponding to 0s in kbi1pe are general-purpose i/o pins that are not associated with the kbi module. 9.4.2 edge and level sensitivity synchronous logic is used to detect edges. prior to detecting an edge, enabled keyboard inputs in a kbi module must be at the deasserted logic level. a falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the i nput signal is seen as a logic 0 during one bus cy cle and then a logic 1 during the next cycle. the kbimod control bit can be set to reconfigure the de tection logic so that it detects edges and levels. in kbimod = 1 mode, the kbf status flag becomes set when an edge is detected (when one or more enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their deasserted levels), but th e flag is continuously set (and cannot be cleared) as long as any enabled keyboard input pin remains at the asserted level. when the mcu enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). in stop mode, kbi inputs act as asynchronous level-sensitive inputs so they can wake the mcu from stop mode. 76543210 r kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 w reset00000000 = unimplemented or reserved figure 9-5. kbi pin enable register (kbi1pe) table 9-2. kbi1pe register field descriptions field description 7:0 kbipe[7:0] keyboard pin enable for kbi port bits ? each of these read/write bits selects whether the associated kbi port pin is enabled as a keyboard interrupt input or functions as a general-purpose i/o pin. 0 bit n of kbi port is a general-purpose i/o pin not associated with the kbi 1 bit n of kbi port enabled as a keyboard interrupt input
keyboard interrupt (s08kbiv1) mc9s08gb60a data sheet, rev. 2 154 freescale semiconductor 9.4.3 kbi interrupt controls the kbf status flag becomes set (1) when an edge event has been detected on any kbi input pin. if kbie = 1 in the kbi1sc register, a hardware interr upt will be requested when ever kbf = 1. the kbf flag is cleared by writing a 1 to the keyboard acknowledge (kback) bit. when kbimod = 0 (selecting edge- only operation), kbf is always cleared by writing 1 to kback. when kbimod = 1 (selecting edge-a nd-level operation), kbf cannot be cleared as long as any keyboard input is at its asserted level.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 155 chapter 10 timer/pwm (s08tpmv1) 10.1 introduction the mc9s08gbxxa/gtxxa includes two independe nt timer/pwm (tpm) modules which support traditional input capture, output compare, or buf fered edge-aligned pulse-wid th modulation (pwm) on each channel. a control bit in each tpm configures all channels in that timer to operate as center-aligned pwm functions. in each of these two tpms, timing functions are based on a separate 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference. this timing system is ideally suited for a wide range of control applications, and the center-aligned pwm capabilit y on the 3-channel tpm extends the fiel d of applications to motor control in small appliances. the use of the fixed system clock, xclk, as the clock source for either of th e tpm modules allows the tpm prescaler to run using the oscillator rate divi ded by two (icgerclk/2). th is clock source must be selected only if the icg is configured in either fbe or fee mode. in fbe mode, this selection is redundant because the busclk frequency is the same as xclk. in fee mode, the proper conditions must be met for xclk to equal icgerclk/2 ( section 7.3.9, ?fixed frequency clock? ). selecting xclk as the clock source with the icg in either fei or scm mode will result in the tpm being non-functional. 10.2 features the timer system in the mc9s08gb xxa includes a 3-channel tpm1 and a separate 5-channel tpm2; the timer system in the mc9s08gtxxa includes two 2- channel modules, tpm1 and tpm2. timer system features include: ? a total of eight channels: ? each channel may be input capture, output compare, or buffered edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? each tpm may be configured fo r buffered, center-aligned pulse-w idth modulation (cpwm) on all channels ? clock source to prescaler for each tpm is inde pendently selectable as bus clock, fixed system clock, or an external pin ? prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 ? 16-bit free-running or up/ down (cpwm) count operation ? 16-bit modulus register to control counter range ? timer system enable ? one interrupt per channel pl us terminal count interrupt
chapter 10 timer/pwm (s08tpmv1) mc9s08gb60a data sheet, rev. 2 156 freescale semiconductor figure 10-1. block diagram highlighting the tpm modules ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 157 10.3 tpm block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?4). the tpm sh ares its i/o pins with general-purpose i/o port pins (refer to the pins and connections chapter for more information). figure 10-2 shows the structure of a tpm. some mcus include more than one tpm, with various numbers of channels. figure 10-2. tpm block diagram the central component of the tpm is the 16-bit count er that can operate as a free-running counter, a modulo counter, or an up-/ down-counter when the tpm is configured for cent er-aligned pwm. the tpm prescale and select 16-bit comparator main 16-bit counter 16-bit comparator 16-bit latch port 16-bit comparator 16-bit latch channel 0 channel 1 internal bus logic interrupt port logic 16-bit comparator 16-bit latch channel n port logic counter reset divide by clock source off, bus, xclk, ext busclk xclk select sync interrupt interrupt interrupt 1, 2, 4, 8, 16, 32, 64, or 128 logic logic logic logic

els0a ch0f els0b els1b els1a elsnb elsna ch1f chnf ch0ie ch1ie chnie ms1b ms0b msnb ms0a ms1a msna . . . . . . . . . tpmxmodh:tpmx tpmx) ext clk tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxcnvh:tpmxcnvl tpmxchn tpmxch1 tpmxch0
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 158 freescale semiconductor counter (when operating in normal up- counting mode) provides the timing reference fo r the input capture, output compare, and edge-aligned pwm functi ons. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter. (the values $0000 or $ffff effectively make the counter free running.) software can read the c ounter value at any time without affecting the counting sequence. a ny write to either byte of the tp mxcnt counter resets the counter regardless of the data value written. all tpm channels are programmabl e independently as input captur e, output compare, or buffered edge-aligned pwm channels. 10.4 pin descriptions table 10-2 shows the mcu pins related to the tpm modul es. when tpmxch0 is used as an external clock input, the associated tpm ch annel 0 can not use the pin. (channel 0 can still be used in output compare mode as a software timer.) when any of the pins associated with the timer is confi gured as a timer input, a passive pullup can be enabled. after reset, th e tpm modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 10.4.1 external tpm clock sources when control bits clksb:clksa in th e timer status and cont rol register are set to 1:1, the prescaler and consequently the 16-bit counter for tpmx are driv en by an external clock source connected to the tpmxch0 pin. a synchronizer is needed between the external clock and the rest of the tpm. this synchronizer is clocked by the bus clock so the frequency of the exte rnal source must be less than one-half the frequency of the bus rate clock. the upper frequency limit for this exte rnal clock source is specified to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (pll) or frequency-locked loop (fll) frequency jitter effects. when the tpm is using the channe l 0 pin for an external clock, th e corresponding els0b:els0a control bits should be set to 0:0 so channel 0 is not trying to use the same pin. 10.4.2 tpmxchn ? tpmx channel n i/o pins each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the configuration of the channel. in some cases, no pin function is needed so the pin reverts to being controlled by general-purpose i/o controls. when a timer has cont rol of a port pin, the port data and data direction registers do not affect the related pin(s). see the pins and connections chapter for additional information about shared pin functions. 10.5 functional description all tpm functions are associ ated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor. a 16-bit m odulo register also is associated w ith the main 16-bit counter in the tpm. each tpm channel is optionally associated with an mcu pin and a maskable interrupt function. the tpm has center-aligned pwm capabilities contro lled by the cpwms control bit in tpmxsc. when cpwms is set to 1, timer counter tpmxcnt changes to an up-/down-counter and all channels in the
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 159 associated tpm act as center-aligned pwm channels. when cpwms = 0, each channel can independently be configured to ope rate in input capture, output compare, or buffered edge-aligned pwm mode. the following sections describe the main 16-bit counter and each of the ti mer operating modes (input capture, output compare, edge-ali gned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 10.5.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, up-counting vs. up-/down-c ounting, end-of-count overflow, and manual counter reset. after any mcu reset, clksb:clksa = 0:0 so no clock source is selected and the tpm is inactive. normally, clksb:clksa would be set to 0:1 so the bus clock drives the timer counter. the clock source for each of the tpm can be independently selected to be off, the bus clock (busclk), the fixed system clock (xclk), or an external in put through the tpmxch0 pin. the ma ximum frequency allowed for the external clock option is one-fourth the bus rate. refer to section 10.7.1, ?timer x status and control register (tpmxsc) ,? and table 10-2 for more information a bout clock source selection. when the microcontroller is in active background mode, the tpm tempor arily suspends al l counting until the microcontroller returns to nor mal user operating mode. during stop mode, all tpm clocks are stopped; therefore, the tpm is effectively disabled until clocks resume. duri ng wait mode, the tpm continues to operate normally. the main 16-bit counter has two counting modes. wh en center-aligned pwm is selected (cpwms = 1), the counter operates in up-/down-counting mode. otherw ise, the counter operates as a simple up-counter. as an up-counter, the main 16-bit counter counts from $0000 through its terminal count and then continues with $0000. the terminal count is $ffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is specified, the counter counts upward from $0000 through its terminal count and then counts downward to $0000 wh ere it returns to up-counting. both $0000 and the terminal count value (value in tpmxmodh:tpmxm odl) are normal length counts (one timer clock period long). an interrupt flag and enable are associated with th e main 16-bit counter. the ti mer overflow flag (tof) is a software-accessible indica tion that the timer counter has overflowed. the enab le signal selects between software polling (toie = 0) where no hardware interrupt is generated, or interrupt-driven operation (toie = 1) where a static hardware interrupt is au tomatically generated whenever the tof flag is 1. the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the main 16-bit counter counts from $0000 through $ffff and overflows to $0000 on the next counting clock. tof becomes set at the tr ansition from $ffff to $0 000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to $0000. when the main 16-bit counter is operating in up-/down-counting mode, th e tof flag gets set as the counter changes direction at the transi tion from the value set in th e modulus register and the next lower count value. this corresponds to the end of a pwm period. (the $0000 c ount value corresponds to the center of a period.)
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 160 freescale semiconductor because the hcs08 mcu is an 8-bit architecture, a c oherency mechanism is built into the timer counter for read operations. whenever either byte of the counter is read (t pmxcnth or tpmxcntl), both bytes are captured into a buffer so when th e other byte is read, the value will represent the ot her byte of the count at the time the first byte was read. the counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. the main timer counter can be reset manually at any time by writing any value to either byte of the timer count tpmxcnth or tpmxcntl. re setting the counter in this ma nner also resets the coherency mechanism in case only one byte of the co unter was read before resetting the count. 10.5.2 channel mode selection provided cpwms = 0 (center-aligned pw m operation is not specified), th e msnb and msna control bits in the channel n status and control registers dete rmine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and buffered edge-aligned pwm. 10.5.2.1 input capture mode with the input capture func tion, the tpm can capture the time at whic h an external event occurs. when an active edge occurs on the pi n of an input capture channel, the tpm latches the contents of the tpm counter into the channel value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge th at triggers an input capture. when either byte of the 16-bit capt ure register is read, both bytes ar e latched into a buffer to support coherent 16-bit accesses regardless of order. the coherency sequence can be manually reset by writing to the channel status/contro l register (tpmxcnsc). an input capture event sets a flag bit (chnf) th at can optionally generate a cpu interrupt request. 10.5.2.2 output compare mode with the output compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reach es the value in the channel value registers of an output compare channel, the tpm can set, clear, or toggle the channel pin. in output compare mode, values are transferred to the corresponding timer cha nnel value registers only after both 8-bit bytes of a 16-bit regi ster have been written. this coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an output compare event sets a flag bit (chnf) th at can optionally generate a cpu interrupt request. 10.5.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer c ounter (cpwms = 0) and can be used when other channels in the same tpm ar e configured for input cap ture or output compare functions. the period of this pwm signal is dete rmined by the setting in the modulus register (tpmxmodh:tpmxmodl). the duty cy cle is determined by the setti ng in the timer channel value
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 161 register (tpmxcnvh:tpmxcn vl). the polarity of this pwm signal is determined by the setting in the elsna control bit. duty cycle cases of 0 percent and 100 percent are possible. as figure 10-3 shows, the output compare va lue in the tpm channel register s determines the pulse width (duty cycle) of the pwm signal. the time between the modulus overf low and the output compare is the pulse width. if elsna = 0, the counter overflow forces the pwm signal high and the output compare forces the pwm signal low. if elsna = 1, the counte r overflow forces the pwm signal low and the output compare forces the pwm signal high. figure 10-3. pwm period and pulse width (elsna = 0) when the channel value register is set to $0000, the dut y cycle is 0 percent. by setting the timer channel value register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting, 100 percent duty cycle can be achieved. this implies that the modulus setting must be less than $ffff to get 100 percent duty cycle. because the hcs08 is a family of 8-bit mcus, the sett ings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widt hs. writes to either register, tpmxcnvh or tpmxcnvl, write to buffer registers. in edge-pwm mode, values are transferred to the corresponding timer channel re gisters only after both 8-bit bytes of a 16-bit register have been written and the value in the tpmxcnth:tpmxcn tl counter is $0000. (the new duty cy cle does not take effect until the next full period.) 10.5.3 center-aligned pwm mode this type of pwm output uses the up-/down-count ing mode of the timer counter (cpwms = 1). the output compare value in tpmxcnvh:tpmxcnvl determ ines the pulse width (duty cycle) of the pwm signal and the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of $0001 to $7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) eqn. 10-1 period = 2 x (tpmxmodh:tpmxmodl); for tpmxmodh:tpmxmodl = $0001?$7fff eqn. 10-2 if the channel value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0 percent. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is grea ter than the (nonzero) modulus setting, the duty cycl e will be 100 percent because the duty cy cle compare will never occur. this implies the usable range of periods set by the modulus register is $0001 through $7ffe ($7fff if period pulse width overflow overflow overflow output compare output compare output compare tpmxc
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 162 freescale semiconductor generation of 100 percent duty cycle is not necessary). this is not a significant limitation because the resulting period is much longer than required for norm al applications. tpmxmodh:tpmxmodl = $0000 is a special case that should not be used wi th center-aligned pwm mode. when cpwms = 0, this case corresponds to the counter runni ng free from $0000 through $ffff, but when cpwms = 1 the counter needs a valid match to the modulus register somewhere other than at $0000 in order to change directions from up-counting to down-counting. figure 10-4 shows the output compare value in the tpm channel registers (multiplied by 2), which determines the pulse widt h (duty cycle) of the cpwm signal. if elsna = 0, the compare match while counting up forces the cpwm output signal low and a compare match while counting down forces the output high. the counter counts up until it reaches the modulo sett ing in tpmxmodh:tpmxmodl, then counts down until it reache s zero. this sets the period equa l to two times tpmxmodh:tpmxmodl. figure 10-4. cpwm period and pulse width (elsna = 0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also require d for some types of motor drives. because the hcs08 is a family of 8-bit mcus, the sett ings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers, tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, act ually write to buffer re gisters. values are transferred to the corresponding timer ch annel registers only afte r both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). this tpmxcnt overflow requirement only applies to pwm channels, not output compares. optionally, when tpmxcnth:tpmxcntl = tpmxm odh:tpmxmodl, the tpm can generate a tof interrupt at the end of this count. the user can choose to reload any number of the pwm buffers, and they will all update simultaneously at the start of a new period. writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo re gisters. writing to tpmxcnsc ca ncels any values written to the channel value registers and resets the c oherency mechanism for tpmxcnvh:tpmxcnvl. period pulse width count = count = 0 output compare (count up) output compare (count down) count = tpmxmodh:tpmx tpm1c tpmxmodh:tpmx 2 x 2 x
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 163 10.6 tpm interrupts the tpm generates an optional interr upt for the main counter overflow a nd an interrupt for each channel. the meaning of channel interrupts depends on the mode of operation for each channel. if the channel is configured for input capture, the in terrupt flag is set ea ch time the selected input capture edge is recognized. if the channel is configur ed for output compare or pwm modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. see the resets, interrupts, and system configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. for each interrupt source in the tpm, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input captur e, or output compare events. this flag may be read (polle d) by software to verify that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. it is the responsibility of user software to perform a sequence of steps to clear the interrupt flag befo re returning from the interrupt service routine. 10.6.1 clearing timer interrupt flags tpm interrupt flags are cleared by a 2- step process that includes a read of the flag bit while it is set (1) followed by a write of 0 to the bit. if a new event is de tected between these two steps, the sequence is reset and the interrupt flag remains set after the second st ep to avoid the possibility of missing the new event. 10.6.2 timer overflow interrupt description the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the 16-bit timer counter count s from $0000 through $ffff and overflows to $0000 on the next counting clock. tof becomes set at the tr ansition from $ffff to $0 000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to $0000. when the counter is operating in up-/down-count ing mode, the tof flag gets set as the counter cha nges direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the $0000 count value corresponds to the center of a period.) 10.6.3 channel event interrupt description the meaning of channel interrupts depends on the cu rrent mode of the channe l (input capture, output compare, edge-aligned pwm, or center-aligned pwm). when a channel is configured as an input capture channel, the elsnb:elsna control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. when the selected edge is detected, the interrupt flag is set. the flag is cleared by the 2-step sequence described in section 10.6.1, ?clearing timer interrupt flags .? when a channel is configured as an output compare chan nel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channe l value register. the flag is cleared by the 2-step sequence described in section 10.6.1, ?clearing ti mer interrupt flags .?
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 164 freescale semiconductor 10.6.4 pwm end-of-duty-cycle events for channels that are configured for pwm operation, there are two possibilities: ? when the channel is configured for edge-aligned pwm, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. ? when the channel is configured for center-ali gned pwm, the timer count matches the channel value register twice during each pw m cycle. in this cpwm case, the channel flag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. the flag is cleared by the 2- step sequence described in section 10.6.1, ?clearing timer interrupt flags .? 10.7 tpm registers and control bits the tpm includes: ? an 8-bit status and control register (tpmxsc) ? a 16-bit counter (tpmxcnth:tpmxcntl) ? a 16-bit modulo register (tpmxmodh:tpmxmodl) each timer channel has: ? an 8-bit status and control register (tpmxcnsc) ? a 16-bit channel value register (tpmxcnvh:tpmxcnvl) refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all tpm registers. th is section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. some mcu systems have more than one tpm, so register names include placeholder charact ers to identify which tpm and which channel is be ing referenced. for example, tpmx cnsc refers to timer (tpm) x, channel n and tpm1c2sc is the status a nd control register fo r timer 1, channel 2.
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 165 10.7.1 timer x status and control register (tpmxsc) tpmxsc contains the overflow status flag and control bits that are used to configure the interrupt enable, tpm configuration, clock sour ce, and prescale divisor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w r e s e t00000000 = unimplemented or reserved figure 10-5. timer x status and control register (tpmxsc) table 10-1. tpmxsc register field descriptions field description 7 tof timer overflow flag ? this flag is set when the tpm counter changes to $0000 after reaching the modulo value programmed in the tpm counter modulo registers. when the tpm is configured for cpwm, tof is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. clear tof by reading the tpm status and control register when to f is set and then writing a 0 to tof. if another tpm overflow occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. reset clears tof. writing a 1 to tof has no effect. 0 tpm counter has not reached modulo value or overflow 1 tpm counter has overflowed 6 toie timer overflow interrupt enable ? this read/write bit enables tpm over flow interrupts. if toie is set, an interrupt is generated when tof equals 1. reset clears toie. 0 tof interrupts inhibited (use software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select ? this read/write bit selects cpwm oper ating mode. reset clears this bit so the tpm operates in up-counting mode for input capture, out put compare, and edge-aligned pwm functions. setting cpwms reconfigures the tpm to operate in up-/down-counting mode for cpwm functions. reset clears cpwms. 0 all tpmx channels operate as input capture, output co mpare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channel?s status and control register 1 all tpmx channels operate in center-aligned pwm mode 4:3 clks[b:a] clock source select ? as shown in table 10-2 , this 2-bit field is used to di sable the tpm system or select one of three clock sources to drive the counter prescaler. th e external source and the xclk are synchronized to the bus clock by an on-chip synchronization circuit. 2:0 ps[2:0] prescale divisor select ? this 3-bit field selects one of eight divisors for the tpm clock input as shown in ta b l e 1 0 - 3 . this prescaler is located after any clock source synchronization or cloc k source selection, so it affects whatever clock source is selected to drive the tpm system.
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 166 freescale semiconductor 10.7.2 timer x counter regi sters (tpmxcnth:tpmxcntl) the two read-only tpm counter regist ers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read . this allows coherent 16-bit reads in either order. the coherency mechanism is automatically restarted by an mcu reset, a write of a ny value to tpmxcnth or tpmxcntl, or any write to the time r status/control re gister (tpmxsc). reset clears the tpm counter registers. table 10-2. tpm clock source selection clksb:clksa tpm clock source to prescaler input 0:0 no clock selected (tpm disabled) 0:1 bus rate clock (busclk) 1:0 fixed system clock (xclk) 1:1 external source (tpmx ext clk) 1 , 2 1. the maximum frequency that is allowed as an ex ternal clock is one-fourth of the bus frequency. 2. when the tpmxch0 pin is selected as the tpm clock source, the corresponding el s0b:els0a control bits should be set to 0:0 so channel 0 does not try to use the same pin for a conflicting function. table 10-3. prescale divisor selection ps2:ps1:ps0 tpm clock source divided-by 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter. r e s e t00000000 figure 10-6. timer x counter register high (tpmxcnth) 76543210 rb i t 7654321b i t 0 w any write to tpmxcntl clears the 16-bit counter. r e s e t00000000 figure 10-7. timer x counter register low (tpmxcntl)
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 167 when background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in wh en the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.7.3 timer x counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counti ng from $0000 at the next clock (cpwms = 0) or starts counting dow n (cpwms = 1), and the overflow fl ag (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits the tof bit and overflow interrupts until the other byte is written. reset sets the tpm count er modulo registers to $0000, which results in a free-running timer counter (modulo disabled). it is good practice to wait fo r an overflow interrupt so both bytes of the modulo regi ster can be written well before a new overflow. an alternative approach is to reset the tpm counter before writing to the tpm modulo registers to avoid conf usion about when the first counter overflow will occur. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 10-8. timer x counter modulo register high (tpmxmodh) 76543210 r bit 7654321bit 0 w reset00000000 figure 10-9. timer x counter modulo register low (tpmxmodl)
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 168 freescale semiconductor 10.7.4 timer x channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 76543210 r chnf chnie msnb msna elsnb elsna 00 w r e s e t00000000 = unimplemented or reserved figure 10-10. timer x channel n status and control register (tpmxcnsc) table 10-4. tpmxcnsc register field descriptions field description 7 chnf channel n flag ? when channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. this flag is seldom used with center-aligned pwms because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. a corresponding interrupt is requested when chnf is se t and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf would remain set after the clear sequence was completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost by clearing a previous chnf. reset clears chnf. writing a 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output com pare event occurred on channel n 6 chnie channel n interrupt enable ? this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n ? when cpwms = 0, msnb = 1 configures tpm channel n for edge-aligned pwm mode. for a summary of channel mode and setup controls, refer to table 10-5 . 4 msna mode select a for tpm channel n ? when cpwms = 0 and msnb = 0, msna configures tpm channel n for input capture mode or output compare mode. refer to ta b l e 1 0 - 5 for a summary of channel mode and setup controls. 3:2 elsn[b:a] edge/level select bits ? depending on the operating mode for the timer channel as set by cpwms:msnb:msna and shown in ta b l e 1 0 - 5 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output comp are match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 configures the related time r pin as a general-purpose i/o pin unrelated to any timer channel functions. this function is typically used to te mporarily disable an input capture channel or to make the timer pin available as a general-purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. this is also the setting required for channel 0 when the tpmxch0 pin is used as an external clock input.
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 169 if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. typica lly, a program would clear status flags after changing channel configuration bits and before enab ling channel interrupts or using the status flags to avoid any unexpected behavior. 10.7.5 timer x channel value registers (tpmxcnvh:tpmxcnvl) these read/write register s contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the cha nnel value registers are cleared by reset. table 10-5. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode configuration xx x 0 0 pin not used for tpm channel; use as an external clock for the tpm or revert to general-purpose i/o 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 00 output compare software compare only 01 toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1x x 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 10-11. timer x channel value register high (tpmxcnvh) 76543210 r bit 7654321bit 0 w reset00000000 figure 10-12. timer channel value register low (tpmxcnvl)
timer/pwm (tpm) mc9s08gb60a data sheet, rev. 2 170 freescale semiconductor in input capture mode, reading eith er byte (tpmxcnvh or tpmxcnvl) la tches the contents of both bytes into a buffer where they remain latched until the ot her byte is read. this latc hing mechanism also resets (becomes unlatched) when the tpmxcnsc register is written. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. this latching me chanism may be manually reset by writing to the tpmxcnsc register. this latching mechanism allows cohe rent 16-bit writes in either orde r, which is friendly to various compiler implementations.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 171 chapter 11 serial communications interface (s08sciv1) 11.1 introduction the mc9s08gbxxa/gtxxa includes tw o independent serial communica tions interface (s ci) modules ? sometimes called universal asynchronous receiver/trans mitters (uarts). typically, these systems are used to connect to the rs 232 serial input/output (i/o) port of a personal computer or workstation, and they can also be used to communicate with other embedded controllers. a flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. transmit and receive within the same sci use a common baud rate, and each sci module has a separate baud rate generator. this sci system offers many adva nced features not commonly found on other asynchronous serial i/o peripherals on other embedded cont rollers. the receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. hardware parity, receiver wakeup, and double buffering on transmit and receive are also included.
chapter 11 serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 172 freescale semiconductor figure 11-1. block diagram highlighting the sci modules ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 173 11.1.1 features features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and re ceiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wakeup by idle-line or address-mark 11.1.2 modes of operation see section 11.3, ?functional description ,? for a detailed description of sci operation in the different modes. ? 8- and 9- bit data modes ? stop modes ? sci is halted during all stop modes ? loop modes
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 174 freescale semiconductor 11.1.3 block diagram figure 11-2 shows the transmitter portion of the sci. ( figure 11-3 shows the receiver portion of the sci.) figure 11-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd enable
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 175 figure 11-3 shows the receiver portion of the sci. figure 11-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 176 freescale semiconductor 11.2 register definition the sci has eight 8-bit registers to control baud ra te, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.2.1 sci baud rate regi sters (scixbdh, scixbhl) this pair of registers co ntrols the prescale diviso r for sci baud rate genera tion. to update the 13-bit baud rate setting [sbr12:sbr0], first writ e to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate genera tor remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). 76543210 r000 sbr12 sbr11 sbr10 sbr9 sbr8 w r e s e t00000000 = unimplemented or reserved figure 11-4. sci baud rate register (scixbdh) table 11-1. scixbdh register field descriptions field description 4:0 sbr[12:8] baud rate modulo divisor ? these 13 bits are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 1 - 2 . 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 figure 11-5. sci baud rate register (scixbdl) table 11-2. scixbdl register field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 1 - 1 .
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 177 11.2.2 sci control register 1 (scixc1) this read/write register is used to contro l various optional features of the sci system. 76543210 r loops sciswai rsrc m wake ilt pe pt w r e s e t00000000 figure 11-6. sci control register 1 (scixc1) table 11-3. scixc1 register field descriptions field description 7 loops loop mode select ? selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ? rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter output s are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci c an be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connecte d to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 3 wake receiver wakeup method select ? refer to section 11.3.3.2, ?recei ver wakeup operation ? for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ? setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. refer to section 11.3.3.2.1, ?idle-line wakeup ? for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable ? enables hardware parity generation and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treat ed as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bi t, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 178 freescale semiconductor 11.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 figure 11-7. sci control register 2 (scixc2) table 11-4. scixc2 register field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 11.3.2.1, ?send break and queued idle ,? for more details. when te is written to 0, the transmitt er keeps control of the port txd pi n until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ? when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 , the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 179 11.2.4 sci status register 1 (scixs1) this register has eight read-only st atus flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. 1 rwu receiver wakeup control ? this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 11.3.3.2, ?rec eiver wakeup operation ,? for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information curr ently being transmitted, a second break character may be queued before software clears sbk. refer to section 11.3.2.1, ?se nd break and queued idle ,? for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w r e s e t11000000 = unimplemented or reserved figure 11-8. sci status register 1 (scixs1) table 11-5. scixs1 register field descriptions field description 7 tdre transmit data register empty flag ? tdre is set immediately after reset and when a transmit data value transfers from the transmit data buffer to the transmit sh ifter, leaving room for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set immediately after reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmi ssion activity complete). tc is cleared automatically by read ing scixs1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scixd) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scixc2 table 11-4. scixc2 register field descriptions (continued) field description
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 180 freescale semiconductor 5 rdrf receive data register full flag ? rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ? idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn?t start counting idle bit times until after the stop bit. so th e stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost bec ause there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag ? the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if an y of these samples disagrees with the rest of the samples within any bit time in the frame, the flag nf will be set at the same time as the flag rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. table 11-5. scixs1 register field descriptions (continued) field description
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 181 11.2.5 sci status register 2 (scixs2) this register has one read-only st atus flag. writes have no effect. 11.2.6 sci control register 3 (scixc3) 76543210 r0000000r a f w r e s e t00000000 = unimplemented or reserved figure 11-9. sci status register 2 (scixs2) table 11-6. scixs2 register field descriptions field description 0 raf receiver active flag ? raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 76543210 rr8 t8 txdir 0 orie neie feie peie w r e s e t00000000 = unimplemented or reserved figure 11-10. sci control register 3 (scixc3) table 11-7. scixc3 register field descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered da ta in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd complete s automatic flag clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd regi ster. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines t he direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 182 freescale semiconductor 11.2.7 sci data register (scixd) this register is actually two separate registers. r eads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and wr ites of this register are also involved in the automatic flag clearing mechanisms for the sci status flags. 3 orie overrun interrupt enable ? this bit enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noise flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 76543210 rr 7r 6r 5r 4r 3r 2r 1r 0 wt 7t 6t 5t 4t 3t 2t 1t 0 r e s e t00000000 figure 11-11. sci data register (scixd) table 11-7. scixc3 register field descriptions (continued) field description
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 183 11.3 functional description the sci allows full-duplex, as ynchronous, nrz serial communica tion among the mcu and remote devices, including other mcus. the sc i comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver opera te independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following desc ribes each of the blocks of the sci. 11.3.1 baud rate generation as shown in figure 11-12 , the clock source for the sci baud ra te generator is the bus-rate clock. figure 11-12. sci baud rate generation sci communications require the transmitter and re ceiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolera nce on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundari es on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mi smatch is about 4.5 percent for 8-bit data format and about 4 percent for 9-bit data format. although baud rate modulo divider settings do not always produce baud rates that exactly match st andard rates, it is normally possi ble to get within a few percent, which is acceptable for reliable communications. 11.3.2 transmitter functional description this section describes the overall block diagram for the sci transmitter ( figure 11-2 ), as well as specialized functions for sendi ng break and idle characters. the transmitter is enabled by setting the te bit in sc ixc2. this queues a preamble character that is one full character frame of the id le state. the transmitter then remains idle until data is available in the transmit data buffer. programs store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmit ter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for th e remainder of this section, we will assume m = 0, selecting the normal 8-bi t data mode. in 8-bit data m ode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 184 freescale semiconductor the transmit data register is transfer red to the shift register (synchronized with the ba ud rate clock) and the transmit data register empt y (tdre) status flag is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in th e transmit data buffer after a stop bi t is shifted out the txd1 pin, the transmitter sets the transmit comple te flag and enters an idle mode, with txd1 high, waiting for more characters to transmit. writing 0 to te does not immediately release the pin to be a general-pur pose i/o pin. any tr ansmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 11.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is av ailable. if sbk is still 1 when the queued break moves into the shifter (s ynchronized to the baud rate clock) , an additional break character is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifte r, then write 0 and then write 1 to the te bit. this action queues an idle ch aracter to be sent as soon as the shifter is available. as long as the character in the shifter does not finish while te = 0, the sci transmitter never actually releases control of the txd1 pin. if there is a possibility of the shif ter finishing while te = 0, set the gene ral-purpose i/o controls so the pin that is shared with txd1 is an output driving a logic 1. this ensures that the txd1 line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. 11.3.3 receiver functional description in this section, the data sampling technique used to r econstruct receiver data is described in more detail; two variations of the receiver wa keup function are explained. (the r eceiver block diagram is shown in figure 11-3 .) the receiver is enabled by se tting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb firs t), and a stop bit of logic 1. for info rmation about 9-bit data mode, refer to section 11.3.5.1, ?8- and 9-bit data modes .? for the remainder of this discussion, we assume the sci is configured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive da ta register and the receive data register full (rdrf) status flag is set. if rdrf was already se t indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. because the sci re ceiver is double-buffered, the
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 185 program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user?s program that handles receive data. refer to section 11.3.4, ?interrupts and status flags ,? for more details about flag clearing. 11.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiv er starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd1 serial data input pin. a falling edge is defined as a logic 0 sample after thre e consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a fa lling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit a nd not merely noise. if at least two of these three samples ar e 0, the receiver assumes it is s ynchronized to a receive character. the receiver then samples each bi t time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in th e case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including th e start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (nf) will be set wh en the received character is transferred to the receive data buffer. the falling edge detection l ogic continuously looks for fall ing edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhe re in the character frame. in the case of a framing error, pr ovided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new charac ters until the framing error flag is cleared. the receive shift register continues to f unction, but a complete character cannot transfer to the receive data buffer if fe is still set. 11.3.3.2 receiver wakeup operation receiver wakeup is a hardware mech anism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu = 1, it inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for handling the unimportant messa ge characters. at the end of a messag e, or at the beginning of the next message, all receivers automa tically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 186 freescale semiconductor 11.3.3.2.1 idle-line wakeup when wake = 0, the receiver is configured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detect s a full character time of the idle-l ine level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle ar e needed to constitute a full character time (10 or 11 bit times becaus e of the start and stop bits). when the rwu bit is set, the idle character that wa kes a receiver does not set th e receiver idle bit, idle, or the receive data register full fl ag, rdrf. it therefore will not gene rate an interrupt when this idle character occurs. the receiver will wake up and wait for the next data transmi ssion which will set rdrf and generate an interrupt if enabled. the idle-line type (ilt) control bit se lects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit a nd any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 11.3.3.2.2 address-mark wakeup when wake = 1, the receiver is configured for a ddress-mark wakeup. in this mode, rwu is cleared automatically when the receiver detect s a logic 1 in the most significant bi t of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but re quires that the msb be reserved for use in address frames. the logic 1 msb of an a ddress frame clears the receivers rwu bit before the stop bit is received and sets the rdrf flag. 11.3.4 interrupts and status flags the sci system has three se parate interrupt vectors to reduce the amount of softwa re needed to isolate the cause of the interrupt. one interrupt vector is associated with th e transmitter for tdre and tc events. another interrupt vector is associat ed with the receiver for rdrf and idle events, and a third vector is used for or, nf, fe, and pf error conditions. each of these eight interrupt sources can be separately masked by local interrupt enable masks. the flags can still be polled by software when the local masks are cleared to disable ge neration of hardware interrupt requests. the sci transmitter has two status fl ags that optionally can generate hard ware interrupt re quests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (t c) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with txd1 high. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a hardwa re interrupt will be requested whenever tc = 1. instead of hardware interrupts, software polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared by reading scixs1 while rdrf = 1 and then reading scixd.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 187 when polling is used, this sequence is naturally satisfied in the normal course of the user program. if hardware interrupts are used, scixs1 mu st be read in the interrupt servi ce routine (isr). normally, this is done in the isr anyway to check for receive erro rs, so the sequence is automatically satisfied. the idle status flag includes logi c that prevents it from getting set repeatedly when the rxd1 line remains idle for an extended period of time. idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cl eared, it cannot become set again unt il the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe) , and parity error flag (pf) ? get set at the same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is rea dy to be transferred from the receive shifter to the receive data buffer, the overrun (or) flag gets set instead and the data and any associated nf, fe, or pf condition is lost. 11.3.5 additional sci functions the following sections descri be additional sci functions. 11.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be conf igured to operate in 9-bi t data mode by setting the m control bit in scixc1. in 9-bit m ode, there is a ninth data bit to th e left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transm itted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker. 11.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci regist er data is lost and must be re-initialized upon reco very from these two stop modes. no sci module registers are affected in stop3 mode. because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software should ensure stop mode is not entere d while there is a character being transmitted out of or received into the sci module.
serial communications interface (s08sciv1) mc9s08gb60a data sheet, rev. 2 188 freescale semiconductor 11.3.5.3 loop mode when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is someti mes used to check software, independent of connections in the external system, to help isolate system pr oblems. in this mode, the transmitter output is internally connected to the receiver input and the rx d1 pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 11.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). single- wire mode is used to implemen t a half-duplex serial connection. the receiver is internally connected to the transmit ter output and to the txd1 pin. the rxd1 pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the txdi r bit in scixc3 controls the direction of serial data on the txd1 pin. when txdir = 0, the txd1 pin is an input to the sci receiver and the transmitt er is temporarily disconnected from the txd1 pin so an external device can send serial data to th e receiver. when txdir = 1, the txd1 pin is an output driven by the tran smitter. in single-wire mode, the in ternal loop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 189 chapter 12 serial peripheral interface (s08spiv3) 12.1 introduction the mc9s08gbxxa/gtxxa provides one serial peripheral interface (spi) module. the four pins associated with spi functionality ar e shared with port e pins 2?5. see the appendix a, ?electrical characteristics ,? appendix for spi electrica l parametric information. when the spi is enabled, the direction of pins is contro lled by module configuration. if the spi is disabled, all f our pins can be used as general-purpose i/o.
chapter 12 serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 190 freescale semiconductor figure 12-1. block diagram highlighting the spi module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 191 12.1.1 features features of the spi module include: ? master or slave mode operation ? full-duplex or single-w ire bidirectional option ? programmable transmit bit rate ? double-buffered transmit and receive ? serial clock phase and polarity options ? slave select output ? selectable msb-first or lsb-first shifting 12.1.2 block diagrams this section includes block diagrams showing spi system c onnections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 12.1.2.1 spi system block diagram figure 12-2 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master sh ifts data out (on th e mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input (ss pin). in this system, the mast er device has c onfigured its ss pin as an optional slave select output. figure 12-2. spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 192 freescale semiconductor the most common uses of the spi system include c onnecting simple shift regi sters for adding input or output ports or connecting small pe ripheral devices such as serial a/d or d/a converters. although figure 12-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transfer red from the master mcu to a slave or from a slave to the master mcu. 12.1.2.2 spi module block diagram figure 12-3 is a block diagram of the spi module. the central element of th e spi is the spi shift register. data is written to the d ouble-buffered transmitter (wri te to spi1d) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spi1d). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is configured as a master, the clock out put is routed to the spsc k pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is configured as a slave, the spsck pin is routed to the clock i nput of the spi, the shifter output is routed to miso, and the shifte r input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins.
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 193 figure 12-3. spi module block diagram 12.1.3 spi baud rate generation as shown in figure 12-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) di vide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr tx buffer (write spi1d) rx buffer (read spi1d)
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 194 freescale semiconductor figure 12-4. spi baud rate generation 12.2 external signal description the spi optionally shares four port pi ns. the function of these pins depe nds on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins re vert to being general-pur pose port i/o pins that are not controlled by the spi. 12.2.1 spsck ? spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. wh en the spi is enabled as a master, this pin is the serial clock output. 12.2.2 mosi ? master data out, slave data in when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc 0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master m ode is selected, this pin becomes the bidirectional data i/o pin (mom i). also, the bidirecti onal mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a gene ral-purpose port i/o pin. 12.2.3 miso ? master da ta in, slave data out when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enable d as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is se lected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bid iroe = 1). if spc0 = 1 and ma ster mode is selected, this pin is not used by the spi and reve rts to being a general-purpose port i/o pin. 12.2.4 ss ? slave select when the spi is enabled as a slave, this pin is the lo w-true slave select input. wh en the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not us ed by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modf en = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 195 12.3 modes of operation 12.3.1 spi in stop modes the spi is disabled in all stop mode s, regardless of the settings befo re executing the stop instruction. during either stop1 or stop2 mode, th e spi module will be fully powered down. upon wake-up from stop1 or stop2 mode, the spi module will be in the reset st ate. during stop3 mode, cloc ks to the spi module are halted. no registers are affected. if st op3 is exited with a reset, the spi wi ll be put into its reset state. if stop3 is exited with an interrupt, the spi continues from the state it was in when stop3 was entered. 12.4 register definition the spi has five 8-bit registers to select spi options, control ba ud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to register s and control bits only by their names, and a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.4.1 spi control register 1 (spi1c1) this read/write register includes the spi enable control, interrupt enables, and configuration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w r e s e t00000100 figure 12-5. spi control register 1 (spi1c1) table 12-1. spi1c1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ? this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable ? disabling the spi halts any trans fer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ? this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 196 freescale semiconductor note ensure that the spi should not be disa bled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur. 12.4.2 spi control register 2 (spi1c2) this read/write register is used to control optional featur es of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. 4 mstr master/slave mode select 0 spi module configured as a slave spi device 1 spi module configured as a master spi device 3 cpol clock polarity ? this bit effectively places an inverter in series with the clock signal from a master spi or to a slave spi device. refer to section 12.5.1, ?spi clock formats ? for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ? this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 12.5.1, ?spi clock formats ? for more details. 0 first edge on spsck occurs at the middle of the first cycle of an 8-cycle data transfer 1 first edge on spsck occurs at the start of the first cycle of an 8-cycle data transfer 1 ssoe slave select output enable ? this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) contro l bit to determine the function of the ss pin as shown in table 12-2 . 0 lsbfe lsb first (shifter direction) 0 spi serial data transfers start with most significant bit 1 spi serial data transfers start with least significant bit table 12-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10s s input for mode fault slave select input 1 1 automatic ss output slave select input 76543210 r000 modfen bidiroe 0 spiswai spc0 w r e s e t00000000 = unimplemented or reserved figure 12-6. spi control register 2 (spi1c2) table 12-1. spi1c1 field descriptions (continued) field description
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 197 12.4.3 spi baud rate register (spi1br) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 12-3. spi1c2 register field descriptions field description 4 modfen master mode-fault function enable ? when the spi is configured for sl ave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in mast er mode, this bit determines how the ss pin is used (refer to ta b l e 1 2 - 2 for more details). 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ? when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is configured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/ o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 ? the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data tr ansfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 0 spi uses separate pins for data input and data output 1 spi configured for single-wire bidirectional operation 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w r e s e t00000000 = unimplemented or reserved figure 12-7. spi baud rate register (spi1br) table 12-4. spi1br register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor ? this 3-bit field selects one of eight divisors for the spi baud rate prescaler as shown in ta b l e 1 2 - 5 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 12-4 ). 2:0 spr[2:0] spi baud rate divisor ? this 3-bit field selects one of eight diviso rs for the spi baud rate divider as shown in ta b l e 1 2 - 6 . the input to this divider comes from the spi baud rate prescaler (see figure 12-4 ). the output of this divider is the spi bit rate clock for master mode.
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 198 freescale semiconductor 12.4.4 spi status register (spi1s) this register has three read-only st atus bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0. writes have no meaning or effect. table 12-5. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 12-6. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf 0 sptef modf 0 0 0 0 w r e s e t00100000 = unimplemented or reserved figure 12-8. spi status register (spi1s)
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 199 12.4.5 spi data register (spi1d) reads of this register return the data read from the rece ive data buffer. writes to th is register write data to the transmit data buffer. when the spi is configured as a master, writi ng data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buf fer unless the spi transmit buffer empty flag (sptef) is set, indicating there is room in the transmit buffer to queue a new transmit byte. data may be read from spi1d any ti me after sprf is set and before anot her transfer is finished. failure to read the data out of the receive data buffer before a new transfer ends causes a recei ve overrun condition and the data from the new transfer is lost. table 12-7. spi1s register field descriptions field description 7 sprf spi read buffer full flag ? sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spi 1d). sprf is cleared by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer 1 data available in the receive data buffer 5 sptef spi transmit buffer empty flag ? this bit is set when there is room in the transmit data buffer. it is cleared by reading spi1s with sptef set, followed by writing a data value to the transmit buffer at spi1d. spi1s must be read with sptef = 1 before writing data to spi1d or the spi1d write will be igno red. sptef generates an sptef cpu interrupt request if the sptie bit in the spi1 c1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shi ft register. for an idle spi (no data in the transmit buffer or the shift register and no transfer in progress), data written to spi1d is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bi t data value to be queued into the transmit buffer. after completion of the transfer of the va lue in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef will be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ? modf is set if the spi is configured as a master and the slave select input goes low, indicating some other spi device is also configured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spi1c1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 7654321bit 0 w reset00000000 figure 12-9. spi data register (spi1d)
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 200 freescale semiconductor 12.5 functional description an spi transfer is initiated by checking for the spi transmit buffer empty flag (sptef = 1) and then writing a byte of data to the spi data register (spi1d) in the master spi device. when the spi shift register is available, this byte of data is m oved from the transmit data buffer to th e shifter, sptef is set to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on th e miso pin at one spsck e dge and shifted, changing the bit value on the mosi pin, one-half spsck cycle la ter. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the master?s shift re gister. at the end of this transfer, the received data byte is moved from the shifter into th e receive data buffer and sprf is set to indicate the da ta can be read by reading spi1d. if another byte of da ta is waiting in the transmit buffe r at the end of a transfer, it is moved into the shifter, sptef is set, and a new transfer is started. normally, spi data is transferred most significant bit (msb) first. if th e least significant bit first enable (lsbfe) bit is set, spi data is shifted lsb first. when the spi is configur ed as a slave, its ss pin must be driven low befo re a transfer starts and ss must stay low throughout the tran sfer. if a clock format wh ere cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see section 12.5.1, ?spi clock formats ? for more details. because the transmitter a nd receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffe r, and a previously rece ived character can be in the receive data buffer while a new character is being shifted in. the sptef flag indicates when the transmit buffer has room for a new character. the sprf flag indicates when a received character is available in the receive data buffer. the received char acter must be read out of the receive buffer (read spi1d) before the next transfer is fini shed or a receive overrun error results. in the case of a receive overrun, the new data is lo st because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 12.5.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from differen t manufacturers, the spi system has a clock polarity (cpol) bi t and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol se lectively inserts an inverter in series with the clock. cpha chooses between two different clock phase rela tionships between the clock and data. figure 12-10 shows the clock formats when cpha = 1. at th e top of the figure, th e eight bit times are shown for reference with bit 1 st arting at the first spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb first and ls b first lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are show n, but only one of these waveforms applies for a specific transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slav e or the miso input of a master. the mosi waveform applies to the
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 201 mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bi t time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 12-10. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not defined until the first spsck edge. the first spsck edge shifts the first bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi input s, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slave?s ss input is not required to go to its inactive high level between transfers. figure 12-11 shows the clock formats when cpha = 0. at th e top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (ss in goes low), and bit 8 ends at the last spsck edge. the msb first and lsb fi rst lines show the order of spi data bits dependi ng on the setting bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 202 freescale semiconductor in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the va lue in cpol. the sample in wave form applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso wavefo rm applies to the miso out put from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the fi rst bit time of the transfer and goe s back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 12-11. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the first data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the first spsck edge causes both the master and the slave to sample the data bit valu es on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was ju st sampled and shifts the second data bit value out the other end of the shifte r to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slave?s ss input must go to its in active high level between transfers. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 203 12.5.2 spi interrupts there are three flag bits, two interr upt mask bits, and one interrupt vect or associated with the spi system. the spi interrupt enable mask (spie) enables interrupt s from the spi receiver full flag (sprf) and mode fault flag (modf). the spi transm it interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty fl ag (sptef). when one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated flag bits instead of using inte rrupts. the spi interrupt se rvice routine (isr) should check the flag bits to de termine what event caused the interrupt. the service routine should also clear the flag bit(s) before returning from the is r (usually near the beginning of the isr). 12.5.3 mode fault detection a mode fault occurs and th e mode fault flag (modf) becomes set wh en a master spi device detects an error on the ss pin (provided the ss pin is configured as the m ode fault input signal). the ss pin is configured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection f eature can be used in a system where mo re than one spi de vice might become a master at the same t ime. the error is detect ed when a master?s ss pin is low, indicating that some other spi device is trying to addre ss this master as if it were a slave. th is could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all spi output driver s when such an error is detected. when a mode fault is detected, modf is set and mstr is cleared to change the spi configuration back to slave mode. the output drivers on the spsck, mo si, and miso (if not bi directional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spi1c1). user software should verify the error condition has been corrected before changing the spi back to master mode.
serial peripheral interface (s08spiv3) mc9s08gb60a data sheet, rev. 2 204 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 205 chapter 13 inter-integrated circuit (s08iicv1) 13.1 introduction the mc9s08gbxxa/gtxxa series of microcontrollers provides one inte r-integrated circuit (iic) module for communication with other integr ated circuits. the two pins associ ated with this module, sda1 and scl1 share port c pins 2 a nd 3, respectively. all functi onality as described in th is section is available on mc9s08gbxxa/gtxxa. when the iic is enabled, th e direction of pins is controlled by module configuration. if the iic is disabled, both pins can be us ed as general-purpose i/o.
chapter 13 inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 206 freescale semiconductor figure 13-1. block diagram highlighting the iic module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 207 13.1.1 features the iic includes these distinctive features: ? compatible with iic bus standard ? multi-master operation ? software programmable for one of 64 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection 13.1.2 modes of operation the iic functions the same in normal and monitor modes. a brief description of the iic in the various mcu modes is given here. ? run mode ? this is the basic mode of operation. to conserve pow er in this mode, disable the module. ? wait mode ? the module wi ll continue to operate while the mc u is in wait mode and can provide a wake-up interrupt. ? stop mode ? the iic is inactive in stop3 mode for reduced power consumption. the stop instruction does not affect iic register states. stop2 and stop1 will reset the register contents.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 208 freescale semiconductor 13.1.3 block diagram figure 13-2 is a block diagram of the iic. figure 13-2. iic functional block diagram 13.2 external signal description this section describes each user-accessible pin signal. 13.2.1 scl ? serial clock line the bidirectional scl is the serial clock line of the iic system. 13.2.2 sda ? serial data line the bidirectional sda is the serial data line of the iic system. 13.3 register definition this section consists of the iic register descriptions in address order. input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 209 refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 iic address register (iic1a) 13.3.2 iic frequency divider register (iic1f) 76543210 r addr 0 w r e s e t00000000 = unimplemented or reserved figure 13-3. iic address register (iic1a) table 13-1. iic1a register field descriptions field description 7:1 addr[7:1] iic address register ? the addr contains the specific slave addres s to be used by the iic module. this is the address the module will respond to when addressed as a slave. 76543210 r mult icr w reset00000000 figure 13-4. iic frequency divider register (iic1f)
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 210 freescale semiconductor table 13-2. iic1f register field descriptions field description 7:6 mult iic multiplier factor ? the mult bits define the multiplier factor mul. this factor is used along with the scl divider to generate the iic baud rate. the multiplier factor mul as defined by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5:0 icr iic clock rate ? the icr bits are used to prescale the bus cloc k for bit rate selection. these bits are used to define the scl divider and the sda hold value. the scl divider multiplied by the value provided by the mult register (multiplier factor mul) is used to generate iic baud rate. iic baud rate = bus speed (hz)/(mul * scl divider) sda hold time is the delay from the falling edge of the scl (i ic clock) to the changing of sda (iic data). the icr is used to determine the sda hold value. sda hold time = bus period (s) * sda hold value ta b l e 1 3 - 3 provides the scl divider and sda hold values for corresponding values of the icr. these values can be used to set iic baud rate and sda hold time. for example: bus speed = 8 mhz mult is set to 01 (mul = 2) desired iic baud rate = 100 kbps iic baud rate = bus speed (hz)/(mul * scl divider) 100000 = 8000000/(2*scl divider) scl divider = 40 ta b l e 1 3 - 3 shows that icr must be set to 0b to provide an sc l divider of 40 and that this will result in an sda hold value of 9. sda hold time = bus period (s) * sda hold value sda hold time = 1/8000000 * 9 = 1.125 s if the generated sda hold value is not acceptable, the mult bits can be used to change the icr. this will result in a different sda hold value.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 211 table 13-3. iic divider and hold values icr (hex) scl divider sda hold value icr (hex) scl divider sda hold value 00 20 7 20 160 17 01 22 7 21 192 17 02 24 8 22 224 33 03 26 8 23 256 33 04 28 9 24 288 49 05 30 9 25 320 49 06 34 10 26 384 65 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 0a 36 9 2a 448 65 0b 40 9 2b 512 65 0c 44 11 2c 576 97 0d 48 11 2d 640 97 0e 56 13 2e 768 129 0f 68 13 2f 960 129 10 48 9 30 640 65 11 56 9 31 768 65 12 64 13 32 896 129 13 72 13 33 1024 129 14 80 17 34 1152 193 15 88 17 35 1280 193 16 104 21 36 1536 257 17 128 21 37 1920 257 18 80 9 38 1280 129 19 96 9 39 1536 129 1a 112 17 3a 1792 257 1b 128 17 3b 2048 257 1c 144 25 3c 2304 385 1d 160 25 3d 2560 385 1e 192 33 3e 3072 513 1f 240 33 3f 3840 513
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 212 freescale semiconductor 13.3.3 iic control register (iic1c) 76543210 r iicen iicie mst tx txak 000 w rsta r e s e t00000000 = unimplemented or reserved figure 13-5. iic control register (iic1c) table 13-4. iic1c register field descriptions field description 7 iicen iic enable ? the iicen bit determines whether the iic module is enabled. 0 iic is not enabled. 1 iic is enabled. 6 iicie iic interrupt enable ? the iicie bit determines whethe r an iic interrupt is requested. 0 iic interrupt request not enabled. 1 iic interrupt request enabled. 5 mst master mode select ? the mst bit is changed from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0slave mode. 1 master mode. 4 tx transmit mode select ? the tx bit selects the direct ion of master and slave transfers. in master mode this bit should be set according to the type of transfer required. therefore, for addr ess cycles, this bit will always be high. when addressed as a slave this bit should be set by softwar e according to the srw bit in the status register. 0 receive. 1 transmit. 3 txak transmit acknowledge enable ? this bit specifies the value driven onto the sda during data acknowledge cycles for both master and slave receivers. 0 an acknowledge signal will be sent out to the bus after receiving one data byte. 1 no acknowledge signal response is sent. 2 rsta repeat start ? writing a one to this bit will generate a repeated start condition provided it is the current master. this bit will always be read as a low. attempting a rep eat at the wrong time will result in loss of arbitration.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 213 13.3.4 iic status register (iic1s) 76543210 rtcf iaas busy arbl 0srw iicif rxak w r e s e t10000000 = unimplemented or reserved figure 13-6. iic status register (iic1s) table 13-5. iic1s register field descriptions field description 7 tcf transfer complete flag ? this bit is set on the completion of a byte transfer. note that this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iic1d register in receive mode or writing to the iic1d in transmit mode. 0 transfer in progress. 1 transfer complete. 6 iaas addressed as a slave ? the iaas bit is set when the calling add ress matches the programmed slave address. writing the iic1c register clears this bit. 0 not addressed. 1 addressed as a slave. 5 busy bus busy ? the busy bit indicates the status of the bus r egardless of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle. 1 bus is busy. 4 arbl arbitration lost ? this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software, by writing a one to it. 0 standard bus operation. 1 loss of arbitration. 2 srw slave read/write ? when addressed as a slave the srw bit indicates the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave. 1 slave transmit, master reading from slave. 1 iicif iic interrupt flag ? the iicif bit is set when an interrupt is pendi ng. this bit must be cleared by software, by writing a one to it in the interrupt routine. on e of the following events can set the iicif bit: ? one byte transfer completes ? match of slave address to calling address ? arbitration lost 0 no interrupt pending. 1 interrupt pending. 0 rxak receive acknowledge ? when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received. 1 no acknowledge received.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 214 freescale semiconductor 13.3.5 iic data i/o register (iic1d) note when transmitting out of master receive mode, the ii c mode should be switched before reading the iic1d re gister to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are avai lable after an addres s match has occurred. note that the tx bit in iic1c must correctly reflect the desired directi on of transfer in master and slave modes for the transmission to begin. fo r instance, if the iic is configured for master transm it but a master receive is desired, then reading the iic1d will not initiate the receive. reading the iic1d will return the last byte received while the iic is confi gured in either master receive or slave receive modes. the iic1d doe s not reflect every byte that is transmitted on the iic bus, nor can software verify that a byte has been written to the iic1d correctly by reading it back. in master transmit mode, the first byte of data written to iic1d foll owing assertion of ms t is used for the address transfer and should comprise of the calling address (in bit 7?bit 1) concatenat ed with the required r/w bit (in position bit 0). 76543210 r data w r e s e t00000000 figure 13-7. iic data i/o register (iic1d) table 13-6. iic1d register field descriptions field description 7:0 data data ? in master transmit mode, when data is written to the iic1d, a data transfer is initiated. the most significant bit is sent first. in master receive mode, reading th is register initiates receiving of the next byte of data.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 215 13.4 functional description this section provides a complete func tional description of the iic module. 13.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for da ta transfer. all devices connected to it must have open drain or open collec tor outputs. a logic and function is exercised on both lines with external pull-up resistors. the va lue of these resistors is system dependent. normally, a standard communication is composed of four parts: ? start signal ? slave address transmission ? data transfer ? stop signal the stop signal should not be confused with the cpu stop instruction. the iic bus system communication is described briefly in the following sections and illustrated in figure 13-8 . figure 13-8. iic bus transmission signals scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 216 freescale semiconductor 13.4.1.1 start signal when the bus is free; i.e., no mast er device is engaging the bus (bot h scl and sda lines are at logical high), a master may initiate communicati on by sending a start signal. as shown in figure 13-8 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transf er (each data transfer may contain several bytes of da ta) and brings all slaves out of their idle states. 13.4.1.2 slave address transmission the first byte of data transferred immediately after the start signal is the slave address transmitted by the master. this is a seven-bit call ing address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling address that matche s the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pul ling the sda low at the 9th clock (see figure 13-8 ). no two slaves in the system may have the same a ddress. if the iic module is the master, it must not transmit an address that is equal to its own slave a ddress. the iic cannot be mast er and slave at the same time. however, if arbitrati on is lost during an address cycle, the iic will revert to slave mode and operate correctly even if it is being addressed by another master. 13.4.1.3 data transfer before successful slave addressing is achieved, the da ta transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 13-8 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at th e ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowle dge the master in the 9th bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsu ccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is abor ted and the master does one of two things: ? relinquishes the bus by generating a stop signal. ? commences a new calling by gene rating a repeated start signal.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 217 13.4.1.4 stop signal the master can terminate the comm unication by generating a stop signa l to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-hi gh transition of sda while scl at logical 1 (see figure 13-8 ). the master can generate a stop ev en if the slave has generated an acknowledge at which point the slave must release the bus. 13.4.1.5 repeated start signal as shown in figure 13-8 , a repeated start signal is a start si gnal generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a cl ock synchronization proce dure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the c ontending masters is determin ed by a data arbitration procedure, a bus master lose s arbitration if it transm its logic 1 while another ma ster transmits logic 0. the losing masters immediately switch ove r to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not generate a stop condition. me anwhile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. th e devices start counting their low pe riod and after a device?s clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 13-9 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no differen ce between the device cl ocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 218 freescale semiconductor figure 13-9. iic clock synchronization 13.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 13.4.1.9 clock stretching the clock synchronization mechanism ca n be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive sc l low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 13.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 13.6 interrupts the iic generates a single interrupt. an interrupt from the iic is generated when any of the events in table 13-7 occur provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by softwa re by writing a one to it in the interrupt routine. the user can determine the interrupt type by reading the status register. table 13-7. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie scl1 scl2 scl internal counter reset delay start counting high period
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 219 13.6.1 byte transfer interrupt the tcf (transfer complete flag) bit is set at the fa lling edge of the 9th clock to indicate the completion of byte transfer. 13.6.2 address detect interrupt when the calling address matches the programmed slave address (iic address register), the iaas bit in the status register is set. the cp u is interrupted provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 13.6.3 arbitration lost interrupt the iic is a true mul ti-master bus that allows more than one mast er to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of th e contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt wh en it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in th e following circumstances: ? sda sampled as a low when the master drives a high during an address or data transmit cycle. ? sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by so ftware by writing a one to it.
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 220 freescale semiconductor 13.7 initialization/application information figure 13-10. iic module quick start module initialization (slave) 1. write: iica ? to set the slave address 2. write: iicc ? to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 13-11 module initialization (master) 1. write: iicf ? to set the iic baud rate (example provided in this chapter) 2. write: iicc ? to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 13-11 5. write: iicc ? to enable tx 6. write: iicc ? to enable mst (master mode) 7. write: iicd ? with the address of the target slave. (the lsb of this byte will determine whether the communication is master receive or transmit.) module use the routine shown in figure 13-11 can handle both master and slave iic operations. for slave operation, an incoming iic message that contains the proper address will begin iic communication. for master operation, communication must be initiated by writing to the iicd register. 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc iicen iicie mst module configuration arbl 0 srw iicif rxak iics tcf iaas busy module status flags register model addr address to which the module will respond when addressed as a slave (in slave mode) mult icr iicd data data register; write to transmit iic data read to read iic data
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 221 figure 13-11. typical iic interrupt routine clear master mode ? tx/rx ? last byte tr a n s m i t t e d ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0)
inter-integrated circuit (s08iicv1) mc9s08gb60a data sheet, rev. 2 222 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 223 chapter 14 analog-to-digital converter (s08atdv3) the mc9s08gbxxa/gtxxa provides one 8-channel an alog-to-digital (atd) module. the eight atd channels share port b. each channe l individually can be configured for general-purpose i/o or for atd functionality. all features of the atd module as described in this section are available on the mc9s08gbxxa/gtxxa. electrical parametric information for the atd may be found in appendix a, ?electrical characteristics .?
chapter 14 analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 224 freescale semiconductor figure 14-1. mc9s08gb60a block diag ram highlighting atd block and pins ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso1 pte2/ss1 pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module iic module serial peripheral interface module user flash user ram (gx60a = 4096 bytes) debug module (gx60a = 61,268 bytes) hcs08 core note: not all pins are bonded out in all packages. see table 2-2 for complete details. 3-channel timer/pwm module ptb7/ad1p7? port b pte5/spsck1 pte4/mosi1 pte6 pte7 interface module hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd low-power oscillator internal clock generator reset analog-to-digital converter (10-bit) interface module serial communications 5-channel timer/pwm module port f ptf7?ptf0 ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg7?ptg4 (gx32a = 32,768 bytes) (gx32a = 2048 bytes) cpu ( dbg ) ( kbi1 ) ( atd1 ) ( iic1 ) ( sci2 ) ( tpm2 ) ( tpm1 ) ( spi1 ) ( sci1 ) ( icg ) 8 8 scl1 sda1 scl1 scl1 5 3 spsck1 mosi1 miso1 ss1 rxd1 txd1 v ssad v ddad v refh v refl extal xtal bkgd bdc 4 irq = not connected in 48-, 44-, and 42-pin packages = not connected in 44- and 42-pin packages = not connected in 42-pin packages block diagram symbol key:
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 225 14.1 introduction the atd module is an analog-to-digital converter with a successive appr oximation register (sar) architecture with sample and hold. 14.1.1 features ? 8-/10-bit resolution ? 14.0 sec, 10-bit single convers ion time at a conversion frequency of 2 mhz ? left-/right-justified result data ? left-justified signed data mode ? conversion complete flag or conversion complete interrupt generation ? analog input multiplexer for up to eight analog input channels ? single or continuous conversion mode 14.1.2 modes of operation the atd has two modes for low power ? stop mode ? power-down mode 14.1.2.1 stop mode when the mcu goes into stop mode, the mcu stops the cl ocks and the atd analog circuitry is turned off, placing the module into a low-power state. once in stop mode, the atd module aborts any single or continuous conversion in progress. upon exiting stop mode, no conversions occur and the registers have their previous values. as long as the atdpu bit is set prior to entering stop mode, the module is reactivated coming out of stop. 14.1.2.2 power down mode clearing the atdpu bit in register atd1c also plac es the atd module in a low-power state. the atd conversion clock is disabled and the analog circuitr y is turned off, placing the module in power-down mode. (this mode does not remove power to the atd module.) once in power-down mode, the atd module aborts any conversi on in progress. upon setting the atdpu bi t, the module is reactivated. during power-down mode, the atd registers are still accessible. note that the reset state of the atdpu bit is zero. th erefore, the module is rese t into the power-down state. 14.1.3 block diagram figure 14-2 illustrates the functional structure of the atd module.
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 226 freescale semiconductor figure 14-2. atd block diagram 14.2 signal description 14.2.1 overview the atd supports eight input channels and requires 4 supply/reference/g round pins. these pins are listed in table 14-1 . address control r/w data ctl data justification interrupt conversion register sar_reg <9:0> conversion clock prescaler busclk clock prescaler ctl status state machine conversion mode control block control and registers ctl result registers input mux = internal pins = chip pads v ddad v ss v ssad v dd ad1p0 ad1p1 ad 1p 2 ad1p3 ad1p4 ad1p5 ad 1p 6 ad1p7 v refl v refh analog digital powerdown successive approximation register analog-to-digital converter (atd) block status
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 227 14.2.1.1 channel input pins ? ad1p7?ad1p0 the channel pins are used as the analog input pins of the atd. each pin is connected to an analog switch which serves as the signal gate into the sample submodule. 14.2.1.2 atd reference pins ? v refh , v refl these pins serve as the source for the high and low reference potentials for the converter. separation from the power supply pins accommodates th e filtering necessary to achieve the accuracy of which the system is capable. 14.2.1.3 atd supply pins ? v ddad , v ssad these two pins are used to supply power and ground to the analog section of the atd. dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on digital power supplies. note v ddad1 and v dd must be at the same potential. likewise, v ssad1 and v ss must be at the same potential. 14.3 functional description the atd uses a successive approximatio n register (sar) architecture. th e atd contains all the necessary elements to perform a single analog-to-digital conversion. a write to the atd1sc register initiates a new conv ersion. a write to the atd1c register will interrupt the current conversion but it will not initiate a new conversion. a write to the atd1pe register will also abort the current conve rsion but will not in itiate a new conversion. if a c onversion is already running when a write to the atd1sc register is made, it wi ll be aborted and a ne w one will be started. 14.3.1 mode control the atd has a mode control unit to communicate with the sample a nd hold (s/h) machine and the sar machine when necessary to collect samples and perform conversions. the mode control unit signals the s/h machine to begin collecting a sample and for th e sar machine to begin receiving a sample. at the end of the sample period, the s/h machine signals the sar machine to begin the analog-to-digital conversion process. the conversion process is terminated when the sar machine signals the end of table 14-1. signal properties name function ad7?ad0 channel input pins v refh high reference voltage for atd converter v refl low reference voltage for atd converter v ddad atd power supply voltage v ssad atd ground supply voltage
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 228 freescale semiconductor conversion to the mode control unit. for v refl and v refh , the sar machine uses the reference potentials to set the sampled signal level within itself without relying on the s/h machine to deliver them. the mode control unit organi zes the conversion, specifies the input sa mple channel, and moves the digital output data from the sar register to th e result register. the re sult register consists of a dual-port register. the sar register writes data into the register th rough one port while the module data bus reads data out of the register through the other port. 14.3.2 sample and hold the s/h machine accepts analog signals and stores them as capacitor ch arge on a storage node located in the sar machine. only one sample can be held at a time so the s/h machine and the sar machine can not run concurrently even though they are i ndependent machines. figure 14-3 shows the placement of the various resistors and capacitors. figure 14-3. resistor and capacitor placement when the s/h machine is not sampling, it disables it s own internal clocks.the input analog signals are unipolar. the signals must fall wi thin the potential range of v ssad to v ddad . the s/h machine is not required to perform special conversions (i.e., convert v refl and v refh ). proper sampling is dependent on the following factors: ? analog source impedance (the real portion, r as ? see appendix a, ?electrical characteristics ? ) ? this is the resistive (or real, in the case of high frequencies) portion of the network driving the analog input voltage v ain . ? analog source capacitance (c as ) ? this is the filte ring capacitance on the analog input, which (if large enough) may help the analog source networ k charge the atd input in the case of high r as . ? atd input resistance (r ain ? maximum value 7 k ) ? this is the internal resistance of the atd circuit in the path between the external atd input and the atd sample and hold circuit. this resistance varies with temperature, voltage, and process variation but a worst case number is necessary to compute wors t case sample error. + r ain1 r as c as c ain r ain2 r ain3 r ainn atd sar engine channel select 0 channel select 1 channel select 2 channel select n . . . input pin input pin input pin input pin ? v ain
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 229 ? atd input capacitance (c ain ? maximum value 50 pf) ? this is the internal capacitance of the atd sample and hold circuit. this capacitance varies with te mperature, voltage, and process variation but a worst case number is necessa ry to compute worst case sample error. ? atd conversion clock frequency (f at d c l k ? maximum value 2 mhz) ? th is is the frequency of the clock input to the atd and is dependent on the bus clock frequency and the atd prescaler. this frequency determines the width of th e sample window, which is 14 atdclk cycles. ? input sample frequency (f samp ? see appendix a, ?electri cal characteristics ?) ? this is the frequency that a given input is sampled. ? delta-input sample voltage ( v samp ) ? this is the difference betw een the current input voltage (intended for conversion) and the previously sa mpled voltage (which may be from a different channel). in non-continuous convert mode, th is is assumed to be the greater of (v refh ? v ain ) and (v ain ? v refl ). in continuous convert mode, 5 lsb s hould be added to the known difference to account for leakage and other losses. ? delta-analog input voltage ( v ain ) ? this is the difference betw een the current input voltage and the input voltage during the last conversion on a gi ven channel. this is based on the slew rate of the input. in cases where there is no external filtering capacita nce, the sampling error is determined by the number of time constants of charging and the change in input voltage relati ve to the resolution of the atd: # of time constants ( ) = (14 / f atdclk ) / ((r as + r ain ) * c ain ) eqn. 14-1 sampling error in lsb (e s ) = 2 n * ( v samp / (v refh - v refl )) * e ? the maximum sampling error (assuming maximu m change on the input voltage) will be: e s = (3.6/3.6) * e ?(14/((7 k + 10 k) * 50 p * 2 m)) * 1024 = 0.271 lsb eqn. 14-2 in the case where an external filt ering capacitance is applied, the sa mpling error can be reduced based on the size of the source capacitor (c as ) relative to the anal og input capacitance (c ain ). ignoring the analog source impedance (r as ), c as will charge c ain to a value of: e s = 2 n * ( v samp / (v refh ? v refl )) * (c ain / (c ain + c as )) eqn. 14-3 in the case of a 0.1 f c as , a worst case sampling error of 0.5 lsb is achieved regardless of r as . however, in the case of repeat ed conversions at a rate of f samp , r as must re-charge c as . this recharge is continuous and c ontrolled only by r as (not r ain ), and reduces the overall sampling error to: e s = 2 n * {( v ain / (v refh ? v refl )) * e ? (1 / (f samp * r as * c as ) + ( v samp / (v refh - v refl )) * min[(c ain / (c ain + c as )), e ? (1 / (f atdclk * (r as + r ain ) * c ain ) ]} eqn. 14-4 this is a worst case sampling er ror which does not account for r as recharging the combination of c as and c ain during the sample window. it does illustrate that high values of r as (>10 k ) are possible if a large c as is used and sufficient time to recharge c as is provided between samples. in order to achieve accuracy specified under the worst case conditions of maximum v samp and minimum c as , r as must be less than the maximum value of 10 k . the maximum value of 10 k for r as is to ensure low sampling error in the worst case condition of maximum v samp and minimum c as .
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 230 freescale semiconductor 14.3.3 analog input multiplexer the analog input multiplexer selects one of the eight external analog input channels to generate an analog sample. the analog input multiplexer includes negative stress protection circuitry which prevents cross-talk between channels when the applied input pot entials are within specif ication. only analog input signals within the pot ential range of v refl to v refh (atd reference potentials) will result in valid atd conversions. 14.3.4 atd module accuracy definitions figure 14-4 illustrates an ideal atd transfer function. th e horizontal axis represents the atd input voltage in millivolts. the vertical axis the conversion result code. the atd is specified with the following figures of merit: ? number of bits (n) ? the number of bits in the digitized output ? resolution (lsb) ? the resolution of the atd is the step size of the ideal transfer function. this is also referred to as the ideal code width, or the difference between the transition voltages to a given code and to the next code. th is unit, known as 1lsb, is equal to 1lsb = (v refh ? v refl ) / 2 n eqn. 14-5 ? inherent quantiz ation error (e q ) ? this is the error caused by the division of the perfect ideal straight-line transfer function into the quantized ideal transfer function with 2 n steps. this error is 1/2 lsb. ? differential non-linearity (dnl) ? this is the di fference between the curr ent code width and the ideal code width (1lsb). the curr ent code width is the difference in the transition voltages to the current code and to the next code . a negative dnl means the transf er function spends less time at the current code than ideal; a positive dnl, more. the dnl cannot be less than ?1.0; a dnl of greater than 1.0 reduces the effective number of bits by 1. ? integral non-linearity (inl) ? th is is the difference between the transition voltage to the current code and the transition to the corresponding code on the adjusted transfer curve. inl is a measure of how straight the line is (how far it deviates fr om a straight line). the adjusted ideal transition voltage is: eqn. 14-6 ? zero scale error (e zs ) ? this is the difference between the tr ansition voltage to the first valid code and the ideal transition to that code. normally, it is defined as the difference between the actual and ideal transition to code 0x001, but in some cases th e first transition may be to a higher code. the ideal transition to any code is: eqn. 14-7 (current code - 1/2) 2 n adjusted ideal trans. v = * ((v refh + e fs ) - (v refl + e zs )) (current code - 1/2) ideal transition v = 2 n *(v refh ? v refl )
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 231 ? full scale error (e fs ) ? this is the difference between the tr ansition voltage to the last valid code and the ideal transition to that code. normally, it is defined as the difference between the actual and ideal transition to code 0x3ff, but in some cases the last transition may be to a lower code. the ideal transition to any code is: eqn. 14-8 ? total unadjusted error (e tu ) ? this is the difference between th e transition voltage to a given code and the ideal straight-line transfer function. an al ternate definition (with th e same result) is the difference between the actual transfer function and the ideal stra ight-line transfer function. this measure of error includes inhere nt quantization error and all fo rms of circuit error (inl, dnl, zero-scale, and full-scale) except input leakage error, which is not due to the atd. ? input leakage error (e il ) ? this is the error between the tran sition voltage to the current code and the ideal transition to that code that is the result of input leakage acro ss the real portion of the impedance of the network that drives the analog input. this error is a system-observable error which is not inherent to the atd, so it is not added to total error. this error is: e il (in v) = input leakage * r as eqn. 14-9 there are two other forms of error which are not specified which can al so affect atd accuracy. these are: ? sampling error (e s ) ? the error due to inadequate t ime to charge the atd circuitry ? noise error (e n ) ? the error due to noise on v ain , v refh , or v refl due to either direct coupling (noise source capacitively coupled directly on the signal) or power supply (v ddad , v ssad , v dd , and v ss ) noise interfering with the atd? s ability to resolve the input accurately. the error due to internal sources can be reduced (and specif ied operation achieved) by operating the atd conversion in wait mode and ceasi ng all io activity. reducing the erro r due to external sources is dependent on system activity and board layout. (current code - 1/2) ideal transition v = 2 n *(v refh ? v refl )
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 232 freescale semiconductor figure 14-4. atd accuracy definitions 4 8 12 0 1 2 3 4 5 6 7 8 9 a b c total unadjusted ideal straight-line ideal transfer 3 2 1 lsb d code transfer function function total unadjusted inl (assumes e zs =e fs =0) error boundary negative dnl (code width <1lsb) positive dnl (code width >1lsb) error at this code 1 lsb quantization error notes: graph is for example only and may not represent actual performance
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 233 14.4 resets the atd module is reset on system reset. if the sy stem reset signal is activated, the atd registers are initialized back to their reset stat e and the atd module is powered down. this occurs as a function of the register file initialization; the re set definition of the atdpu bit (power down bit) is zero or disabled. the mcu places the module back into an initialized state. if the module is performing a conversion, the current conversion is terminated, the conversion complete flag is cleared, and the sar register bits are cleared. any pending interrupts are also cancelled. note that the control, test, and status registers are initialized on reset; the initialized register state is defined in the register de scription section of this specification. enabling the module (using the atdpu bit) does not cause the module to reset since th e register file is not initialized. finally, writing to control register atd1c does not cause the module to reset; the current conversion will be terminated. 14.5 interrupts the atd module originates interrupt requests and the mcu handl es or services thes e requests. details on how the atd interrupt requests are handled can be found in chapter 5, ?resets, interrupts, and system configuration ?. the atd interrupt function is enable d by setting the atdie bit in the atd1sc register. when the atdie bit is set, an interrupt is genera ted at the end of an at d conversion and the atd re sult registers (atd1rh and atd1rl) contain the result data generated by th e conversion. if the interr upt function is disabled (atdie = 0), then the ccf flag must be polled to determine when a conversion is complete. the interrupt will remain pending as long as the ccf flag is set. the ccf bit is cl eared whenever the atd status and control (atd1sc) register is written. the ccf bit is also cleared whenever the atd result registers (atd1rh or atd1rl) are read. 14.6 atd registers and control bits the atd has seven registers which control atd functions. refer to the direct-page register summary in chapter 4, ?memory ? of this data sheet for the absolute address assignments for all atd registers. this secti on refers to registers and control bits only by their names. a freescale-provided equate or header file is used to tr anslate these names into the appropriate absolute addresses. table 14-2. interrupt summary interrupt local enable description ccf atdie conversion complete
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 234 freescale semiconductor 14.6.1 atd control (atdc) writes to the atd control register will abort the current conversion, but will not start a new conversion. 76543210 r atdpu djm res8 sgn prs w reset00000000 figure 14-5. atd control register (atd1c) table 14-3. atd1c field descriptions field description 7 at d p u atd power up ? this bit provides program on/off control ov er the atd, reducing power consumption when the atd is not being used. when cleared, the atdpu bit aborts any conversion in progress. 0 disable the atd and enter a low-power state. 1 atd functionality. 6 djm data justification mode ? this bit determines how the 10-bit conversi on result data maps onto the atd result register bits. when res8 is set, bit djm has no ef fect and the 8-bit result is always located in atd1rh. see section 14.6.3, ?atd result data (atd1rh, atd1rl) ,? fo r d e t a i l s. the effect of the djm bit on the result is shown in ta bl e 1 4 - 4 . 0 result register data is left justified. 1 result register data is right justified. 5 res8 atd resolution select ? this bit determines the resolution of t he atd converter, 8-bits or 10-bits. the atd converter has the accuracy of a 10-bit converter. howeve r, if 8-bit compatibility is required, selecting 8-bit resolution will map result data bits 9-2 onto atd1rh bits 7-0 . the effect of the res8 bit on the result is shown in table 14-4 . 0 10-bit resolution selected. 1 8-bit resolution selected. 4 sgn signed result select ? this bit determines whether the result will be signed or unsigned data. signed data is represented as 2?s complement data and is achieved by complementing the msb of the result. signed data mode can be used only when the result is left justified (djm = 0) and is not available for right-justified mode (djm = 1). when a signed result is selected, the range for conver sions becomes ?512 (0x200) to 511 (0x1ff) for 10-bit resolution and ?128 (0x80) to 127 (0x7f) for 8-bit resolution. the effect of the sgn bit on the result is shown in ta b l e 1 4 - 4 . 0 left justified result data is unsigned. 1 left justified result data is signed. 3:0 prs prescaler rate select ? this field of bits determines the pres caled factor for the atd conversion clock. ta b l e 1 4 - 5 illustrates the divide-by operation and the appropriate range of bus clock frequencies.
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 235 table 14-4. available result data formats res8 djm sgn data formats of result analog input v refh =v dda , v refl =v ssa atd1rh:atd1rl v dda v ssa 1 0 0 8-bit : left justified : unsigned 0xff:0x00 0x00:0x00 1 0 1 8-bit : left justified : signed 0x7f:0x00 0x80:0x00 11 x 1 1 the sgn bit is only effective when djm = 0. when djm = 1, sgn is ignored. 8-bit : left justified 2 : unsigned 2 8-bit results are always in atd1rh. 0xff:0x00 0x00:0x00 0 0 0 10-bit : left justified : unsigned 0xff:0xc0 0x00:0x00 0 0 1 10-bit : left justified : signed 0x7f:0xc0 0x80:0x00 01 x 1 10-bit : right justified : unsigned 0x03:0xff 0x00:0x00
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 236 freescale semiconductor 14.6.2 atd status and control (atd1sc) writes to the atd status and control register cl ears the ccf flag, cancels any pending interrupts, and initiates a new conversion. table 14-5. clock prescaler values prs factor = (prs +1) 2 max bus clock mhz (2 mhz max atd clock) 1 1 maximum atd conversion clock frequency is 2 mhz. the max bus clock frequency is computed from the max atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 0, max bus clock = 2 (max atd conversion clock frequency) 2 (factor) = 4 mhz. max bus clock mhz (1 mhz max atd clock) 2 2 use these settings if the maximum desired atd conversion clock frequency is 1 mhz. the max bus clock frequency is computed from the max atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 0, max bus clock = 1 (max atd conversion clock frequency) 2 (factor) = 2 mhz. min bus clock 3 mhz (500 khz min atd clock) 3 minimum atd conversion clock frequency is 500 khz. the min bus clock frequency is computed from the min atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 1, min bus clock = 0.5 (min atd conversion clock frequency) 2 (factor) = 1 mhz. 0 0 0 02421 0 0 0 14842 0010 6 12 6 3 0011 8 16 8 4 0100 10 20 10 5 0101 12 20 12 6 0110 14 20 14 7 0111 16 20 16 8 1000 18 20 18 9 1001 20 20 20 10 1010 22 20 20 11 1011 24 20 20 12 1100 26 20 20 13 1101 28 20 20 14 1110 30 20 20 15 1111 32 20 20 16 76543210 rccf atdie atdco atdch w r e s e t00000001 = unimplemented or reserved figure 14-6. atd status and control register (atd1sc)
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 freescale semiconductor 237 14.6.3 atd result data (atd1rh, atd1rl) for left-justified mode, result da ta bits 9?2 map onto bits 7?0 of atd1 rh, result data bits 1 and 0 map onto atd1rl bits 7 and 6, where bit 7 of at d1rh is the most significant bit (msb). table 14-6. atd1sc field descriptions field description 7 ccf conversion complete flag ? the ccf is a read-only bit which is set each time a conversion is complete. the ccf bit is cleared whenever the atd1sc register is wri tten. it is also cleared whenever the result registers, atd1rh or atd1rl, are read. 0 current conversion is not complete. 1 current conversion is complete. 6 at d i e atd interrupt enabled ? when this bit is set, an interrupt is generated upon completion of an atd conversion. at this time, the result registers contain the result dat a generated by the conversion. the interrupt will remain pending as long as the conversion complete flag ccf is se t. if the atdie bit is cleared, then the ccf bit must be polled to determine when the conver sion is complete. note that system reset clea rs pending interrupts. 0 atd interrupt disabled. 1 atd interrupt enabled. 5 atdco atd continuous conversion ? when this bit is set, the atd will convert samples continuously and update the result registers at the end of each conversion. when this bit is cleared, only one conversion is completed between writes to the atd1sc register. 0 single conversion mode. 1 continuous conversion mode. 4:0 at d c h analog input channel select ? this field of bits selects the analog input channel whose signal is sampled and converted to digital codes. ta b l e 1 4 - 7 lists the coding used to select the various analog input channels. table 14-7. analog input channel select coding atdch analog input channel 00 ad0 01 ad1 02 ad2 03 ad3 04 ad4 05 ad5 06 ad6 07 ad7 08?1d reserved (default to v refl ) 1e v refh 1f v refl
analog-to-digital converter (s08atdv3) mc9s08gb60a data sheet, rev. 2 238 freescale semiconductor figure 14-7. left-justified mode for right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of atd1rh, result data bits 7?0 map onto atd1rl bits 7?0, where bit 1 of at d1rh is the most significant bit (msb). figure 14-8. right-justified mode the atd 10-bit conversion results are stored in two 8-bit result registers, atd1rh and atd1rl. the result data is formatted either left or right justified where the format is selected using the djm control bit in the atd1c register. the 10-bit result data is mapped either between atd1rh bits 7?0 and atd1rl bits 7?6 (left justified), or atd1rh bits 1?0 and atd1rl bits 7?0 (right justified). for 8-bit conversions, the 8-bit result is always lo cated in atd1rh bits 7?0, and the atd1rl bits read 0. for 10-bit conversions, the si x unused bits always read 0. the atd1rh and atd1rl registers are read-only. 14.6.4 atd pin enable (atd1pe) the atd pin enable register allows the pins dedicated to the atd module to be configured for atd usage. a write to this register will abort the current conversion but will not initiate a new conversion. if the atdpex bit is 0 (disabled for atd usage) but the corresponding analog input cha nnel is selected via the atdch bits, the atd will not convert the analog input but will instead convert v refl placing zeroes in the atd result registers. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atd1rh atd1rl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atd1rh atd1rl 76543210 r atdpe7 atdpe6 atdpe5 atdpe4 atdpe3 atdpe2 atdpe1 atdpe0 w reset00000000 figure 14-9. atd pin enable register (atd1pe) table 14-8. atd1pe field descriptions field description 7 atdpe[7:0] atd pin 7?0 enables 0 pin disabled for atd usage. 1 pin enabled for atd usage. result result
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 239 chapter 15 development support 15.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a singl e-wire debug interface to the target mcu that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allo ws non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoint s, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through comma nds fed into the target mcu vi a the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. the alternate bdc clock so urce for mc9s08gbxxa/gtxxa is the icglclk. see chapter 7, ?internal clock generator (s08icgv2) ,? for more information about icgclk and how to select clock sources.
development support mc9s08gb60a data sheet, rev. 2 240 freescale semiconductor 15.1.1 features features of the bdc module include: ? single pin for mode selection and background communications ? bdc registers are not located in the memory map ? sync command to determine target communications rate ? non-intrusive commands for memory access ? active background mode comma nds for cpu register access ? go and trace1 commands ? background command can wake cpu from stop or wait modes ? one hardware address breakpoint built into bdc ? oscillator runs in stop mode, if bdc enabled ? cop watchdog disabled while in active background mode features of the ice system include: ? two trigger comparators: two address + read/write (r/w) or one full address + data + r/w ? flexible 8-word by 16-bit fifo (first-in, first-out) buffe r for capture information: ? change-of-flow addresses or ? event-only data ? two types of breakpoints: ? tag breakpoints for instruction opcodes ? force breakpoints for any address access ? nine trigger modes: ? basic: a-only, a or b ? sequence: a then b ? full: a and b data, a and not b data ? event (store data): event- only b, a then event-only b ? range: inside range (a address b), outside range (address < a or address > b) 15.2 background debug controller (bdc) all mcus in the hcs08 family co ntain a single-wire background debug in terface that supports in-circuit programming of on-chip nonvolatile me mory and sophisticated non-intrus ive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: ? active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands al low the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 241 ? non-intrusive commands can be executed at any time even while the user?s program is running. non-intrusive commands allow a user to read or wr ite mcu memory locations or access status and control registers within the background debug controller. typically, a relatively s imple interface pod is used to translat e commands from a host computer into commands for the custom serial interface to the single-wire bac kground debug system. depending on the development tool vendor, this interface pod may use a sta ndard rs-232 serial port, a parallel printer port, or some other type of communicati ons such as a universal serial bu s (usb) to communicate between the host pc and the pod. the pod typically connects to th e target system with ground, the bkgd pin, reset , and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target syst em or to control startup of a target system before the on-chip nonvolatile memory has be en programmed. sometimes v dd can be used to allow the pod to use power from the target system to a void the need for a separa te power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 15-1. bdm tool connector 15.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communi cation of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the us er?s application program. this pin is also used to request a timed sync respons e pulse to allow a host deve lopment tool to determine the correct clock frequency for b ackground debug serial communications. bdc serial communications use a cu stom serial protocol first introduced on the m68hc12 family of microcontrollers. this protocol a ssumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is in itiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most significant bit first (msb first). for a detailed descript ion of the communications protocol, refer to section 15.2.2, ?communication details .? if a host is attempting to communi cate with a target mcu that ha s an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync res ponse signal from wh ich the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no ex ternal pullup resistor is required. unlike typical open-drain pins, the ex ternal rc time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. the custom prot ocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmfu l drive level conflicts. refer to section 15.2.2, ?communication details ,? for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
development support mc9s08gb60a data sheet, rev. 2 242 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode . when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci fic conditions for forci ng active background depend upon the hcs08 derivative (refer to the introduction to this developm ent support section). it is not necessary to reset the target mcu to communi cate with it through the background debug interface. 15.2.2 communication details the bdc serial interface requires the external contro ller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external cont roller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an extern al controller or by the mcu. data is transferred msb first at 16 bdc clock cycles pe r bit (nominal speed). th e interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecti ng the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and c ontrol register allows th e user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or lo w level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 243 figure 15-2 shows an external host trans mitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0- to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively driv es the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to tr eat the line as an open-drain signal during this period. figure 15-2. bdc ho st-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
development support mc9s08gb60a data sheet, rev. 2 244 freescale semiconductor figure 15-3 shows the host receiving a logic 1 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived star t of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brie f active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level a bout 10 cycles after it started the bit time. figure 15-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 245 figure 15-4 shows the host receiving a logic 0 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by th e target mcu. the host initiates the bit time but the target hcs08 finishes it. because the target wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 bdc clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 15-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
development support mc9s08gb60a data sheet, rev. 2 246 freescale semiconductor 15.2.3 bdc commands bdc commands are sent se rially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-first using a cust om bdc communicat ions protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 15-1 shows all hcs08 bdc commands, a shorthand de scription of their codi ng structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 15-1 to describe the coding stru cture of the bdc commands. commands begin with an 8-bit hexadeci mal command code in the host-to-target direction (most signi ficant bit first) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in th e target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target -to-host direction (fro m bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-tar get direction (for bdcb kpt breakpoint register)
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 247 table 15-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss r ead bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd r ead a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/ rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusiv e c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. re port status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
development support mc9s08gb60a data sheet, rev. 2 248 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to us e for bdc communications until afte r it has analyzed the response to the sync command. to issue a sync command, the host: ? drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscill ator/64 or the self-clocked rate/64.) ? drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) ? removes all drive to the bkgd pin so it reverts to high impedance ? monitors the bkgd pin for the sync response pulse the target, upon detectin g the sync request fr om the host (which is a much longer low time than would ever occur during norma l bdc communications): ? waits for bkgd to re turn to a logic high ? delays 16 cycles to allow the host to stop driving the high speedup pulse ? drives bkgd low for 128 bdc clock cycles ? drives a 1-cycle high speedup pulse to force a fast rise time on bkgd ? removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync res ponse pulse and determines the correct speed for subsequent bdc communications. typically, the hos t can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware br eakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this brea kpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the first instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten ) control bit in the bdc status and control re gister (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is di sabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg ) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the bdc module.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 249 15.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have be en built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status regist ers that are accessible in the user?s memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug module?s functions are used during development, a nd user programs rarely access any of the control and status registers for the debug modul e. the one exception is that the debug system can provide the means to implement a fo rm of rom patching. this topic is discussed in greater detail in section 15.3.6, ?hardware breakpoints .? 15.3.1 comparators a and b two 16-bit comparators (a and b) ca n optionally be qualified with the r/w signal and an opcode tracking circuit. separate control bits a llow you to ignore r/w for each compar ator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opc ode at the specified address is actually executed as opposed to onl y being read from memory into th e instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temp orarily during all bdc accesses. the a comparator is always associated with the 16- bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address pl us data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpu?s write data bus is used. otherwise, the cpu?s read data bus is used. the currently selected trigger mode determines what the debugger logi c does when a comparator detects a qualified match condition. a match can cause: ? generation of a breakpoint to the cpu ? storage of data bus values into the fifo ? starting to store change-of-flow addre sses into the fifo (begin type trace) ? stopping the storage of change-of-flow a ddresses into the fifo (end type trace) 15.3.2 bus capture informat ion and fifo operation the usual way to use the fifo is to setup the trigger mode and other cont rol options, then arm the debugger. when the fifo has filled or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo . status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the inform ation is shifted by one position and
development support mc9s08gb60a data sheet, rev. 2 250 freescale semiconductor the host must perform ((8 ? cnt) ? 1) dummy reads of the fifo to advance it to the first significant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-flow addresses. in these cases, read dbgfh then dbgfl to get one coherent word of info rmation out of th e fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 15.3.5, ?trigger modes ? ), 8-bit data information is stored in to the fifo. in these cases, the high- order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. ea ch time dbgfl is read, the fifo is shifted so the next data value is av ailable through the fifo data port at dbgfl. in trigger modes where the fifo is storing change -of-flow addresses, there is a delay between cpu addresses and the input side of th e fifo. because of this delay, if the trigger event itself is a change-of-flow address or a change-o f-flow address appears during the ne xt two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. the fifo can also be used to generate a profile of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the addr ess of the most-recently fetched opcode to be saved in the fifo. to use the prof iling feature, a host debugger would re ad addresses out of the fifo by reading dbgfh then dbgfl at regul ar periodic intervals. the first eight values would be discarded because they correspond to the eight dbgfl reads needed to initially fill the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 15.3.3 change-of-flow information to minimize the amount of informati on stored in the fifo, only informat ion related to in structions that cause a change to the normal sequential execution of in structions is stored. w ith knowledge of the source and object code program stor ed in the target system, an external debugger system can reconstruct the path of execution through many instruct ions from the change -of-flow information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the a ddress of the conditional br anch opcode). because bra and brn instructions are not conditional, these events do not cause change-o f-flow information to be stored in the fifo. indirect jmp and jsr instruct ions use the current contents of the h: x index register pair to determine the destination address, so the debug system stores the r un-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-flow information. 15.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruc tion opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-flow from a jump, bran ch, subroutine call, or interrupt causes some instructions that have been fetched into the in struction queue to be thrown away without being executed.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 251 a force-type breakpoint wa its for the current instruction to fi nish and then acts upon the breakpoint request. the usual action in respons e to a breakpoint is to go to ac tive background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminolo gy is used in two contexts within the debug module. the first context refers to breakpoint requests from the debug module to the cp u. the second refers to match signals from the comparators to the debugger control logi c. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opc ode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executi ng the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is se parate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 15.3.5 trigger modes the trigger mode controls the overa ll behavior of a debug run. the 4-bi t trg field in th e dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt regi ster, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fi fo begins storing data wh en the qualified trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed unt il the qualified trigger is detected (end trigger). a debug run is started by wr iting a 1 to the arm bit in the dbgc register, which sets the armf flag and clears the af and bf flags and the cnt bits in dbgs. a be gin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event- only modes, the fifo stores change-of-flow addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only tri gger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not n ecessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full m ode trigger because the opcode value is normally known at a particular address. the following trigger mode descripti ons only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali fied with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the si gnal from the comparator with optional r/w qualification is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
development support mc9s08gb60a data sheet, rev. 2 252 freescale semiconductor a-only ? trigger when the address matc hes the value in comparator a a or b ? trigger when the address matches either the value in comparator a or the value in comparator b a then b ? trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any num ber of cycles after the a match and before the b match. a and b data (full mode) ? this is called a full mode because address, data, a nd r/w (optionally) must match within the same bus cycle to cause a tri gger event. comparator a ch ecks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. a and not b data (full mode) ? address must match comparator a, data must not match the low half of comparator b, and r/w mu st match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. event-only b (store data) ? trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) ? after the address has matched the value in comparator a, a trigger event occurs each time the address ma tches the value in comparator b. tr igger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) ? a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ? a trigger occurs when the a ddress is either less than the value in comparator a or greater than the value in comparator b.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 253 15.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 15.3.5, ?trigger modes ,? to be used to gene rate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint reque st will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it ente rs the instruction queue. if a tagged opcode reaches the end of the pipe, th e cpu executes a bgnd in struction to go to active background mode rather than execut ing the tagged opcode. a force-type breakpoint causes the cpu to finish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 15.4 register definition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all dbg regist ers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to tr anslate these names into the appropriate absolute addresses. 15.4.1 bdc registers and control bits the bdc has two registers: ? the bdc status and control regist er (bdcscr) is an 8-bit regist er containing cont rol and status bits for the background debug controller. ? the bdc breakpoint match register (bdcbkpt ) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have a ddresses and cannot be a ccessed by user programs). some of the bits in the bdcscr ha ve write limitations; otherwise, thes e registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents th e ambiguous condition of the contro l bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be wr itten by the write_control serial bdc command. the clock switch (clksw) control bit may be r ead or written at any time.
development support mc9s08gb60a data sheet, rev. 2 254 freescale semiconductor 15.4.1.1 bdc status and c ontrol register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 15-5. bdc status and control register (bdcscr) table 15-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ? typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the deb ug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ? this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ? if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ? when fts = 1, a breakpoint is request ed whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagg ed. if this tagged opcode ever reache s the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ? clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 255 15.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hard ware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and configure the breakpoint logi c. dedicated serial bdc commands (read_bkpt and write_bk pt) are used to read and writ e the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 15.2.4, ?bdc hardware breakpoint .? 15.4.2 system background debug force reset register (sbdfr) this register contains a single write-only contro l bit. a serial background mode command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ? when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force t he target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a backgro und command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status ? this status bit is set if a memory a ccess command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically , the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not conflict with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status ? this status bit is not used in the mc 9s08gbxxa/gtxxa because it does not have any slow access memory. 0 memory access did not conflict with a slow memory access 1 memory access command failed because cpu was not finished with a slow memory access table 15-2. bdcscr register field descriptions (continued) field description
development support mc9s08gb60a data sheet, rev. 2 256 freescale semiconductor figure 15-6. system background debug force reset register (sbdfr) 15.4.3 dbg registers and control bits the debug module includes nine bytes of register spac e for three 16-bit register s and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal applic ation programs. these re gisters are rarely if ever accessed by normal user application programs with the possible ex ception of a rom patching mechanism that uses the breakpoint logic. 15.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high- order eight bits of comparat or a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 15.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low- order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 15.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high- order eight bits of comparat or b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 15.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low- order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. r e s e t00000000 = unimplemented or reserved table 15-3. sbdfr register field description field description 0 bdfr background debug force reset ? a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forc es an mcu reset. this bit cannot be written from a user program.
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 257 15.4.3.5 debug fifo high register (dbgfh) this register provides read- only access to the high-order ei ght bits of the fifo. writes to this register have no meaning or effect. in the event- only trigger modes, the fifo only st ores data into the low-order byte of each fifo word, so this regist er is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 15.4.3.6 debug fifo low register (dbgfl) this register provides read- only access to the low-order ei ght bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the ne xt available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into th e fifo (high-order half of each fifo word is unused). when readi ng 8-bit words out of the fifo, simp ly read dbgfl repeatedly to get successive bytes of data from the fifo. it is n?t necessary to read dbgfh in this case. do not attempt to read data from th e fifo while it is still armed (after arming but before th e fifo is filled or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequenci ng of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodical ly, external host software can develop a prof ile of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the first read. to use the profiling feature, read the fifo eight times without using the data to prime the sequence and then begi n using the data to get a delayed picture of what addresses were be ing executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
development support mc9s08gb60a data sheet, rev. 2 258 freescale semiconductor 15.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset00000000 figure 15-7. debug control register (dbgc) table 15-4. dbgc register field descriptions field description 7 dbgen debug module enable ? used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0dbg disabled 1 dbg enabled 6 arm arm control ? controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ? controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable ? controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparat or(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fi fo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a ? when rwaen = 1, this bit determines whether a read or a write access qualifies comparator a. when rwaen = 0, rw a and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ? controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b ? when rwben = 1, this bit determines whether a read or a write access qualifies comparator b. when rwben = 0, rw b and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ? controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
development support mc9s08gb60a data sheet, rev. 2 freescale semiconductor 259 15.4.3.8 debug trigger register (dbgt) this register can be read any time , but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w r e s e t00000000 = unimplemented or reserved figure 15-8. debug trigger register (dbgt) table 15-5. dbgt regist er field descriptions field description 7 trgsel trigger type ? controls whether the match outputs from com parators a and b are qualified with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparat or a or b must propagate through the opcode tracking logic and a trigger event is on ly signalled to the fifo logi c if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select ? controls whether the fifo starts filling at a trigger or fills in a circular manner until a trigger ends the capture of informati on. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ? selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ? 1111 (no trigger)
development support mc9s08gb60a data sheet, rev. 2 260 freescale semiconductor 15.4.3.9 debug status register (dbgs) this is a read-onl y status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w r e s e t00000000 = unimplemented or reserved figure 15-9. debug status register (dbgs) table 15-6. dbgs register field descriptions field description 7 af trigger match a flag ? af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ? bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag ? while dbgen = 1, this status bit is a read-only im age of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trac e) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count ? these bits are cleared at the start of a debu g run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping trac k of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 261 appendix a electrical characteristics a.1 introduction this section contains electri cal and timing sp ecifications. a.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table a-1 may affect device reliability or cause permanent damage to the de vice. for functional operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table a-1. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1 , 2 , 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. i d 25 ma storage temperature range t stg ?55 to 150 c
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 262 freescale semiconductor a.3 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (h eavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. a-2 solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations 1 and 2 iteratively for any value of t a . table a-2. thermal characteristics rating symbol value unit temp. code operating temperature range (packaged) t a ?40 to 85 cc thermal resistance 64-pin lqfp (gbxxa) 48-pin qfn (gtxxa) 44-pin qfp (gtxxa) 42-pin sdip (gtxxa) ja 1,2 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperat ure, airflow, power dissipation of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the singl e layer board horizontal. single layer board is designed per jedec jesd51-3. 65 82 118 57 c/w ?
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 263 a.4 electrostatic discharge (esd) protection characteristics although damage from static disc harge is much less common on th ese devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd test ing is in conformity with cdf-aec-q00 stress test qualification for automotive grade integrated circuits. (http:// www.aecouncil.com/) this device was qualified to aec-q100 rev e. a device is considered to have faile d if, after exposure to esd pulses, the device no longer meets the device specification requirements. comple te dc parametric and functional testing is performed per the appl icable device specification at r oom temperature followed by hot temperature, unless specified othe rwise in the device specification. a.5 dc characteristics this section includes information about power supply requirements, i/o pin characteristics, and power supply current in various operating modes. table a-3. esd protection characteristics parameter symbol value unit esd target for machine model (mm) mm circuit description v thmm 200 v esd target for human body model (hbm) hbm circuit description v thhbm 2000 v table a-4. dc characteristics (sheet 1 of 3) (temperature range = ?40 to 85 c ambient) parameter symbol min typical 1 max unit supply voltage (run, wait and stop modes.) 0 < f bus < 8 mhz 0 < f bus < 20 mhz v dd 1.8 2.08 3.6 3.6 v minimum ram retention supply voltage applied to v dd v ram 1.0 2 ?v low-voltage detection threshold ? high range (v dd falling) (v dd rising) v lv d h 2.08 2.16 2.1 2.19 2.2 2.27 v low-voltage detection threshold ? low range (v dd falling) (v dd rising) v lv d l 1.80 1.88 1.82 1.90 1.91 1.99 v low-voltage warning threshold ? high range (v dd falling) (v dd rising) v lv w h 2.35 2.35 2.40 2.40 2.5 2.5 v
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 264 freescale semiconductor low-voltage warning threshold ? low range (v dd falling) (v dd rising) v lv w l 2.08 2.16 2.1 2.19 2.2 2.27 v power on reset (por) re-arm voltage (2) mode = stop mode = run and wait v rearm 0.20 0.50 0.30 0.80 0.40 1.2 v input high voltage (v dd > 2.3 v) (all digital inputs) v ih 0.70 v dd ?v input high voltage (1.8 v v dd 2.3 v) (all digital inputs) v ih 0.85 v dd ?v input low voltage (v dd > 2.3 v) (all digital inputs) v il ? 0.35 v dd v input low voltage (1.8 v v dd 2.3 v) (all digital inputs) v il ? 0.30 v dd v input hysteresis (all digital inputs) v hys 0.06 v dd ?v input leakage current (per pin) v in = v dd or v ss, all input only pins |i in | ? 0.025 1.0 a high impedance (off-state) leakage current (per pin) v in = v dd or v ss , all input/output |i oz | ? 0.025 1.0 a internal pullup and pulldown resistors 3 (all port pins and irq) r pu 17.5 52.5 k internal pulldown resistors (port a4?a7 and irq) r pd 17.5 52.5 k output high voltage (v dd 1.8 v) i oh = ?2 ma (ports a, b, d, e, and g) v oh v dd ? 0.5 ? v output high voltage (ports c and f) i oh = ?10 ma (v dd 2.7 v) i oh = ?6 ma (v dd 2.3 v) i oh = ?3 ma (v dd 1.8 v) v dd ? 0.5 ? ? ? maximum total i oh for all port pins |i oht | ?60ma output low voltage (v dd 1.8 v) i ol = 2.0 ma (ports a, b, d, e, and g) v ol ?0 . 5 v output low voltage (ports c and f) i ol = 10.0 ma (v dd 2.7 v) i ol = 6 ma (v dd 2.3 v) i ol = 3 ma (v dd 1.8 v) ? ? ? 0.5 0.5 0.5 maximum total i ol for all port pins i olt ?6 0 m a table a-4. dc characteristics (sheet 2 of 3) (temperature range = ?40 to 85 c ambient) parameter symbol min typical 1 max unit
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 265 figure a-1. pullup and pulldown typical resistor values (v dd = 3.0 v) figure a-2. typical low-side driver (sink) characteristics (ports c and f) dc injection current 4, 5, 6, 7, 8 v in < v ss , v in > v dd single pin limit total mcu limit, includes sum of all stressed pins |i ic | ? ? 0.2 5 ma ma input capacitance (all non-supply pins) (2) c in ?7 p f 1 typicals are measured at 25 c. 2 this parameter is characterized and not tested on each device. 3 measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not cons uming power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values for positive and negative clamp volt ages, then use the larger of the two values. 7 this parameter is characterized and not tested on each device. 8 irq does not have a clamp diode to v dd . do not drive irq above v dd . table a-4. dc characteristics (sheet 3 of 3) (temperature range = ?40 to 85 c ambient) parameter symbol min typical 1 max unit pullup resistor typicals v dd (v) pull-up resistor (k ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 c 85 c ?40 c pulldown resistor typicals v dd (v) pulldown resistance (k ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 c 85 c ?40 c 3.6 typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 c 85 c ?40 c 25 c 85c ?40 c
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 266 freescale semiconductor figure a-3. typical low-side driver (sink) characteristics (ports a, b, d, e, and g) figure a-4. typical high-side driver (source) characteristics (ports c and f) figure a-5. typical high-side (source) characteristics (ports a, b, d, e, and g) typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 c 85 c ?40 c 25 c, i ol = 2 ma 85 c, i ol = 2 ma ?40 c, i ol = 2 ma typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?30 ?25 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?10 ma i oh = ?6 ma i oh = ?3 ma v dd ? v oh (v) 25 c 85 c ?40 c 25 c 85 c ?40 c typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 1 1.2 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ? v oh (v) 25 c 85 c ?40 c 25 c, i oh = 2 ma 85 c, i oh = 2 ma ?40 c, i oh = 2 ma
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 267 a.6 supply current characteristics table a-5. supply current characteristics parameter symbol v dd (v) typical 1 max 2 temp. ( c) run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz) ri dd 3 1.1 ma 2.1 ma 4 2.1 ma (4) 2.1 ma (4) 55 70 85 2 0.8 ma 1.8 ma (4) 1.8 ma (4) 1.8 ma (4) 55 70 85 run supply current (3) measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 3 6.5 ma 7.5 ma (4) 7.5 ma (4) 7.5 ma 5 55 70 85 2 4.8 ma 5.8 ma (4) 5.8 ma (4) 5.8 ma (4) 55 70 85 stop1 mode supply current s1i dd 3 25 na 0.6 a (4) 1.8 a (4) 4.0 a (5) 55 70 85 2 20 na 500 na (4) 1.5 a (4) 3.3 a (4) 55 70 85 stop2 mode supply current s2i dd 3 550 na 3.0 a (4) 5.5 a (4) 11 a (5) 55 70 85 2 400 na 2.4 a (4) 5.0 a (4) 9.5 a (4) 55 70 85 stop3 mode supply current s3i dd 3 675 na 4.3 a (4) 7.2 a (4) 17.0 a (5) 55 70 85 2 500 na 3.5 a (4) 6.2 a (4) 15.0 a (4) 55 70 85 rti adder to stop2 or stop3 6 3 300 na 55 70 85 2 300 na 55 70 85
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 268 freescale semiconductor lvi adder to stop3 (lvdse = lvde = 1) 3 70 a 55 70 85 2 60 a 55 70 85 adder to stop3 for oscillator enabled 7 (oscsten =1) 35 a 55 70 85 25 a 55 70 85 adder for loss-of-clock enabled 3 9 a 55 70 85 1 typicals are measured at 25 c. see ta b l e a - 6 through ta bl e a - 9 for typical curves across voltage/temperature. 2 values given here are preliminary estimates prior to completing characterization. 3 all modules except atd active, icg configured for fbe, and does not include any dc loads on port pins 4 values are characterized but not tested on every part. 5 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. 6 most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 3 v and 422 a at 2v with f bus = 1 mhz. 7 values given under the following conditions: low range operation (range = 0), low power mode (hgo = 0), clock monitor disabled (locd = 1). table a-5. supply current characteristics (continued) parameter symbol v dd (v) typical 1 max 2 temp. ( c)
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 269 figure a-6. typical run i dd for fbe and fee modes, i dd vs v dd figure a-7. typical stop1 i dd 18 16 14 12 10 8 6 4 2 0 i dd (ma) 20 mhz, atd off , fee, 25 c 20 mhz, atd off , fbe, 25 c 8 mhz, atd off , fbe, 25 c 8 mhz, atd off , fee, 25 c 1 mhz, atd off , fee, 25 c 1 mhz, atd off , fbe, 25 c 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.8 v dd (vdc) 2.5 2 1.5 0 400 600 800 1000 1200 v dd (v) stop1 i dd (na) 25 c 200 33 . 5 70 c 85 c 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load.
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 270 freescale semiconductor figure a-8. typical stop 2 i dd figure a-9. typical stop3 i dd 2.5 2 1.5 0 1 1.5 2.5 3 4 v dd (v) stop2 i dd ( a) 25 c 0.5 33 . 5 70 c 85 c 2 3.5 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load. 2.5 2 1.5 0 2 3 5 6 8 v dd (v) stop3 i dd ( a) 25 c 1 33 . 5 70 c 85 c 4 7 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load.
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 271 a.7 atd characteristics table a-6. atd electrical characteristics (operating) no. characteristic condition symbol min typ max unit 1atd supply 1 1 v ddad must be at same potential as v dd . v ddad 1.80 ? 3.6 v 2 atd supply current enabled i ddadrun ?0.71.2 ma disabled (atdpu = 0 or stop) i ddadstop ?0.020.6 a 3 differential supply voltage v dd ?v ddad |v ddlt |? ? 100 mv 4 differential ground voltage v ss ?v ssad |v sdlt |? ? 100 mv 5 reference potential, low |v refl |? ?v ssad v reference potential, high 2.08v < v ddad < 3.6v v refh 2.08 ? v ddad v 1.80v < v ddad < 2.08v v ddad ?v ddad 6 reference supply current (v refh to v refl ) enabled i ref ?200300 a disabled (atdpu = 0 or stop) i ref ? <0.01 0.02 7 analog input voltage 2 2 maximum electrical operating range, not valid conversion range. v indc v ssad ? 0.3 ? v ddad + 0.3 v table a-7. atd timing/performance characteristics 1 no. characteristic condition symbol min typ max unit 1 atd conversion clock frequency 2.08v < v ddad < 3.6v f at d c l k 0.5 ? 2.0 mhz 1.80v < v ddad < 2.08v 0.5 ? 1.0 2 conversion cycles (continuous convert) 2 cc 28 28 <30 atdclk cycles 3 conversion time 2.08v < v ddad < 3.6v t conv 14.0 ? 60.0 s 1.80v < v ddad < 2.08v 28.0 ? 60.0 4 source impedance at input 3 r as ?? 10 k 5 analog input voltage 4 v ain v refl v refh v 6 ideal resolution (1 lsb) 5 2.08v < v ddad < 3.6v res 2.031 ? 3.516 mv 1.80v < v ddad < 2.08v 1.758 ? 2.031 7 differential non-linearity 6 1.80v < v ddad < 3.6v dnl ? + 0.5 + 1.0 lsb 8 integral non-linearity 7 1.80 v < v ddad < 3.6v inl ? + 0.5 + 1.0 lsb
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 272 freescale semiconductor 9 zero-scale error 8 1.80v < v ddad < 3.6v e zs ?+ 0.4 + 1.0 lsb 10 full-scale error 9 1.80v < v ddad < 3.6v e fs ?+ 0.4 + 1.0 lsb 11 input leakage error 10 1.80v < v ddad < 3.6v e il ?+ 0.05 + 5lsb 12 total unadjusted error 11 1.80v < v ddad < 3.6v e tu ?+ 1.1 + 2.5 lsb 1 all accuracy numbers are based on processor and system being in wa it state (very little activity and no io switching) and that adequate low-pass filtering is present on analog input pins (filter with 0.01 f to 0.1 f capacitor between analog input and v refl ). failure to observe these guidelines may result in system or mi crocontroller noise causing accuracy errors which will vary based on board layout and the type and magnitude of the activity. 2 this is the conversion time for subsequent conversions in contin uous convert mode. actual conversion time for single conversion s or the first conversion in continuous mode is extended by one atd cloc k cycle and 2 bus cycles due to starting the conversion a nd setting the ccf flag. the total conversion time in bus cycles for a conversion is: sc bus cycles = ((prs+1) 2) (28+1) + 2 cc bus cycles = ((prs+1) 2) (28) 3 r as is the real portion of the impedance of the network driving th e analog input pin. values greater than this amount may not full y charge the input circuitry of the atd resulting in accuracy error. 4 analog input must be between v refl and v refh for valid conversion. values greater than v refh will convert to 0x3ff less the full scale error (e fs ). 5 the resolution is the ideal step size or 1lsb = (v refh ?v refl )/1024 6 differential non-linearity is the difference between the current code width and the ideal code width (1lsb). the current code w idth is the difference in the transition voltages to and from the current code. 7 integral non-linearity is the difference between the transition vo ltage to the current code and the adjusted ideal transition v oltage for the current code. the adjusted ideal transition voltage is (current code?1/2) (1/((v refh +e fs )?(v refl +e zs ))). 8 zero-scale error is the difference between the transition to t he first valid code and the ideal transition to that code. the id eal transition voltage to a given code is (code?1/2) (1/(v refh ?v refl )). 9 full-scale error is the difference between the transition to the la st valid code and the ideal tr ansition to that code. the ide al transition voltage to a given code is (code?1/2) (1/(v refh ?v refl )). 10 input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pi n. reducing the impedance of the network reduces this error. 11 total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfe r function. this measure of error includes i nherent quantization error (1/2lsb) and circ uit error (differentia l, integral, zero-s cale, and full-scale) error. the specified value of e t assumes zero e il (no leakage or zero real source impedance). table a-7. atd timing/performance characteristics 1 (continued) no. characteristic condition symbol min typ max unit
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 273 a.8 internal clock generation module characteristics table a-8. icg dc electrical specifications (temperature range = ?40 to 85 c ambient) characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit load capacitors c 1 c 2 see note 2 2 see crystal or resonator manufacturer?s recommendation. feedback resistor low range (32k to 100 khz) high range (1m ? 16 mhz) r f 10 1 m m series resistor low range low gain (hgo = 0) high gain (hgo = 1) high range low gain (hgo = 0) high gain (hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 10 20 ? ? ? ? ? ? k icg extal xtal crystal or resonator (see note) c 2 r f c 1 use fundamental mode crystal or ceramic resonator only. note: r s
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 274 freescale semiconductor a.8.1 icg frequency specifications table a-9. icg frequency specifications (v dda = v dda (min) to v dda (max), temperature range = ?40 to 85 c ambient) characteristic symbol min typical max unit oscillator crystal or resonator 4 (refs = 1) (fundamental mode crystal or ceramic resonator) low range high range high gain, fbe (hgo=1,clks = 10) high gain, fee (hgo=1,clks = 11) low power, fbe (hgo=0, clks=10) low power, fee (hgo=0, clks=11) flo fhi_byp fhi_eng flp_byp flp_eng 32 1 2 1 2 ? ? ? ? ? 100 16 10 10 10 khz mhz mhz mhz mhz input clock frequency (clks = 11, refs = 0) low range high range f lo f hi_eng 32 2 ? ? 100 10 khz mhz input clock frequency (clks = 10, refs = 0) f extal 0?4 0m h z internal reference frequency (untrimmed) f icgirclk 182.25 243 303.75 khz duty cycle of input clock 4 (refs = 0) t dc 40 ? 60 % output clock icgout frequency clks = 10, refs = 0 all other cases f icgout f extal (min) f lo (min) f extal (max) f icgdclkmax (max) mhz minimum dco clock (icgdclk) frequency f icgdclkmin 8? m h z maximum dco clock (icgdclk) frequency f icgdclkmax ?40mhz self-clock mode (icgout) frequency 1 f self f icgdclkmin f icgdclkmax mhz self-clock mode reset (icgout) frequency f self_reset 5.5 8 10.5 mhz loss of reference frequency 2 low range high range f lor 5 50 25 500 khz loss of dco frequency 3 f lod 0.5 1.5 mhz crystal start-up time 4, 5 low range high range t cstl t csth ? ? 430 4 ? ? ms fll lock time 4, 6 low range high range t lockl t lockh ? ? 2 2 ms fll frequency unlock range n unlock ?4*n 4*n counts fll frequency lock range n lock ?2*n 2*n counts icgout period jitter, 4, 7 measured at f icgout max long term jitter (averaged over 2 ms interval) c jitter ?0 . 2 % f icg internal oscillator deviation from trimmed frequency 8 v dd = 1.8 ? 3.6 v, (constant temperature) v dd = 3.0 v 10%, ?40 c to 85 c acc int ? ? 0.5 0.5 2 2 %
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 275 figure a-10. internal oscillator deviation from trimmed frequency a.9 ac characteristics this section describes ac ti ming characteristics for each peripheral system. for detailed information about how clocks for the bus are generated, see chapter 7, ?internal clock generator (s08icgv2) .? 1 self-clocked mode frequency is the frequency that the dco generates when the fll is open-loop. 2 loss of reference frequency is the reference frequency detect ed internally, which transitions the icg into self-clocked mode if it is not in the desired range. 3 loss of dco frequency is the dco frequen cy detected internally, which transitions the icg into fll bypassed external mode (if an external reference exists) if it is not in the desired range. 4 this parameter is characterized before qualification rather than 100% tested. 5 proper pc board layout procedures must be followed to achieve specifications. 6 this specification applies to the period of time required for the fll to lock after entering fll engaged internal or external modes. if a crystal/resonator is being used as the refere nce, this specification assumes it is already running. 7 jitter is the average deviation from the programmed frequ ency measured over the specified interval at maximum f icgout . measurements are made with the device powered by filtered su pplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dda and v ssa and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 8 see figure a-10 ?60 ?40 ?20 0 20 20 60 80 100 120 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 0.1 percent (%) temperature ( c) 2 v 3 v
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 276 freescale semiconductor a.9.1 control timing figure a-11. reset timing figure a-12. active background debug mode latch timing table a-10. control timing parameter symbol min typical max unit bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz real-time interrupt internal oscillator period t rti 700 1300 s external reset pulse width 1 1 this is the shortest pulse that is guar anteed to be recognized as a reset pin req uest. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 1.5 x f self_reset ?ns reset low drive 2 2 when any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f self_reset and then samples the level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests. t rstdrv 34 x f self_reset ?ns active background debug mode latch setup time t mssu 25 ? ns active background debug mode latch hold time t msh 25 ? ns irq pulse width 3 3 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypa ssed so shorter pulses can be recognized in that case. t ilih 1.5 x t cyc ?ns port rise and fall time (load = 50 pf) 4 slew rate control disabled slew rate control enabled 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. t rise , t fall ? ? 3 30 ns t extrst reset pin bkgd/ms reset t mssu t msh
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 277 figure a-13. irq timing a.9.2 timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure a-14. timer external clock figure a-15. timer input capture pulse table a-11. tpm input timing function symbol min max unit external clock frequency f tpmext dc f bus /4 mhz external clock period t tpmext 4? t cyc external clock high time t clkh 1.5 ? t cyc external clock low time t clkl 1.5 ? t cyc input capture pulse width t icpw 1.5 ? t cyc t ilih irq t text t clkh t clkl tpmxchn t icpw tpmxchn t icpw tpmxchn
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 278 freescale semiconductor a.9.3 spi timing table a-12 and figure a-16 through figure a-19 describe the timing require ments for the spi system. table a-12. spi timing no. function symbol min max unit operating frequency master slave f op f bus /2048 dc f bus /2 f bus /4 hz 1 sck period master slave t sck 2 4 2048 ? t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 ? ? t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 ? ? t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns 5 data setup time (inputs) master slave t su 15 15 ? ? ns ns 6 data hold time (inputs) master slave t hi 0 25 ? ? ns ns 7 slave access time t a ?1t cyc 8 slave miso disable time t dis ?1t cyc 9 data valid (after sck edge) master slave t v ? ? 25 25 ns ns 10 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 11 rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns 12 fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 279 figure a-16. spi master timing (cpha = 0) figure a-17. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 9 10 11 12 4 9 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss (1) (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 280 freescale semiconductor figure a-18. spi slave timing (cpha = 0) figure a-19. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 freescale semiconductor 281 a.10 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information a bout program/erase operations, see chapter 4, ?memory .? table a-13. flash characteristics characteristic symbol min typical max unit supply voltage for program/erase v prog/erase 1.8 3.6 v supply voltage for read operation 0 < f bus < 8 mhz 0 < f bus < 20 mhz v read 1.8 2.08 3.6 3.6 v internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz internal fclk period (1/fclk) t fcyc 56 . 6 7 s byte program time (random location) (2) t prog 9 t fcyc byte program time (burst mode) (2) t burst 4 t fcyc page erase time 2 2 these values are hardware st ate machine controlled. user code does not ne ed to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc mass erase time (2) t mass 20,000 t fcyc program/erase endurance 3 t l to t h = ?40 c to + 85 c t = 25 c 3 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 100,000 ? ? cycles data retention 4 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additiona l information on how freescale semiconductor defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
appendix a electrical characteristics mc9s08gb60a data sheet, rev. 2 282 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 283 appendix b eb652: migrating from the gb60 series to the gb60a series the following text was taken from freescale semiconductor document eb 652. it is copied here for your conveninece. please see eb652 at freescale.com for th e must up-to-date information regarding ?migrating from the gb60 series to the gb60a series.? b.1 overview this document will explain the differences to be aware of when migrat ing from the mc9s08gb60, mc9s08gb32, mc9s08gt60, and mc9s08gt32 devices to the mc9s08gb60a, mc9s08gb32a, mc9s08gt60a and mc9s08gt32a devices. for the remai nder of this document, gb60 series will refer to the original non-?a? devices and gb60a series will refer to the newer ?a? suffix devices. much of the functionality and performance of the gb60 series and the gb60a series will be identical. however, there are several differen ces designers should understand when migrating to the gb60a series. b.2 flash programming voltage the gb60 series has a minimum v dd requirement for erasi ng and programming the flash, equal to 2.1 v. the gb60a series eliminates this minimum v dd requirement. on the gb60a series, the flash can be programmed and erased across the full operating voltage range of the mcu, or 1.8 v to 3.6 v. b.3 flash block protection: 60k devices only the gb/gt60 flash block protection has a redundant setting. on the gb /gt60a, the redundant setting is used to add a new protection option. on the gb/gt60, when protection is enabled by setti ng the fpdis bit, setting the fps2:fps1:fps0 bits to 1:1:1 protects the same range as 1:1:0, which is loca tions $8000 to $ffff. on the gb/gt60a, setting the fps2:fps1 :fps0 bits to 1:1:0, protects the same range as on the gb/gt60. however, setting the bits to 1:1:1 protects locations $182c to $ffff, leaving locations $1080 to $17ff open to reprogramming. this new protection option is useful for protecting the main user pr ogram area while leaving a small section of 1920 bytes available for data storage. b.4 internal clock generator: high gain oscillator option the gb60 series only has a low-power external oscillator, designed for the low current consumption. the gb60a series has a second external oscillator option: a high gain exte rnal oscillator which provides
appendix b eb652: migrating from the gb60 series to the gb60a series mc9s08gb60a data sheet, rev. 2 284 freescale semiconductor improved noise immunity in the osci llator circuit. the low-power os cillator is also available for power-sensitive applications. this new oscillator option available on the gb60a series is se lected by a new control bit in the icg control register 1 (icgc1): the hg o bit. hgo is bit 7 of th e icgc1 register, formerly an unimplemented bit that always read ?0?. the reset value is ?0?, which select s the low-power oscillator option?which is consistent with the gb60 series external oscillator. setting hgo to ?1? selects the high gain external os cillator which increases the voltage swing across the external crystal or resonator, making it more immune to external noise. the values of the feedback and series resistors for the external oscillator will be different in most cases between hgo=0 and hgo=1. consult the icg dc elect rical specifications tabl e in the mc9s08gb60a data sheet for the proper values. b.5 internal clock generator: low-power oscillator maximum frequency on the gb60 series, the external oscillator?s ma ximum frequency is 10 mhz when in fee mode and 16 mhz when in fbe mode. on the gb60a series, when hgo=1, the same maximum frequencies apply. however, when hgo=0, the maximum frequency is 10 mhz in fee and fbe modes. b.6 internal clock generator: loss-of-clock disable option the icg module has a clock monitor wh ich will generate a loss-of-clock signal when either the reference clock or the dco clock does not meet minimum frequency requirements. this signal is used to generate either a reset or an interrupt, depending on the settings in the icgc2 register. on the gb60 series, this clock monitor cannot be turned on or off by the user. the on/off status of the clock monitor is determined by the state of the icg module. on the gb60a series, an option has been added to al low the user to disable the clock monitor. a new control bit, locd, has been added to the icgc1 regist er at bit position 1, formerly an unimplemented bit. the reset state is ?0?, which enables the clock monito r. setting locd = 1 will disable the clock monitor and thereby eliminate any loss-of -clock resets or interrupts. the advantage of disabling the cloc k monitor is to reduce the current draw of the icg module. disabling the clock monitor when running in stop3 mode with a low-range external oscillator enabled will save approximately 9 a of current. with locd=0 in this configuration, the stop3 i dd is about 14 a. when locd=1 in this configuration, the stop i dd is about 5 a. for the best combination of power conservation and system protection, freescale semiconductor recommends setting the locd=0 whenever the mcu is in active run mode and then setting locd=1 just before entering stop3 mode when oscsten=1. if oscsten=0, then the locd bit will not make a difference in the stop3 current.
appendix b eb652: migrating from the gb60 series to the gb60a series mc9s08gb60a data sheet, rev. 2 freescale semiconductor 285 b.7 system device identification register the system device identification regi ster (sdir) is a 16-bit value that contains a 12-bit pa rt identification number and a 4-bit mask revision number. both the gb60 series and the gb60a series have the same part identification number, $002. the mask revision number for the last production version of the gb60 seri es is $4. the first mask revision number for the gb60a series is $8.
appendix b eb652: migrating from the gb60 series to the gb60a series mc9s08gb60a data sheet, rev. 2 286 freescale semiconductor
mc9s08gb60a data sheet, rev. 2 freescale semiconductor 287 appendix c ordering information and mechanical drawings c.1 ordering information this section contains ordering numbers fo r mc9s08gb60a, mc9s08gb32a, mc9s08gt60a, and mc9s08gt32a devices. see below for an example of the device numbering system. table c-1. device numbering system device number flash memory ram tpm available package type mc9s08gb60a 60k 4k one 3-channel and one 5-channel 16-bit timer 64 lqfp mc9s08gb32a 32k 2k one 3-channel and one 5-channel 16-bit timer 64 lqfp mc9s08gt60a 60k 4k one 3-channel and one 2-channel 16-bit timer 48 qfn two 2-channel/16-bit timers 44 qfp 42 sdip mc9s08gt32a 32k 2k one 3-channel and one 2-channel 16-bit timer 48 qfn two 2-channel/16-bit timers 44 qfp 42 sdip table c-2. package information pin count type designator document no. 64 lqfp ? low quad flat package fu 98ass23234w 48 qfn ? quad flat package, no leads fd 98arh99048a 44 qfp ? quad flat package fb 98asb42839b 42 sdip ? skinny dual in-line package b 98asb42767b mc 9 s08 gb60a c xx package designator temperature range family memory type status core (mc = fully qualified) (9 = flash-based) (c = ?40 c to 85 c) (see table c-2 )
appendix c ordering information and mechanical drawings mc9s08gb60a data sheet, rev. 2 288 freescale semiconductor c.2 mechanical drawings the following pages are me chanical drawings for the packages provided in table c-2 .

mc9s08gb60a rev. 2, 07/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2005-2008. all rights reserved.

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